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mf924-02 S1L35000 series design guide design guide gate array S1L35000 series s t issue march,2000 d m ay, 2001 in japan c a
notice no part of this material may be reproduced or duplicated in any from or by any means without the written permission of epson. epson reserves the right to make changes to this material without notice. epson does not assume any liability of any kind arising out of any inaccuracies contained in this material or due to its application or use in any product or circuit and, further, there is no representation that this material is applicable to products requiring high level reliability, such as, medical products. moreover, no license to any intellectual property rights is granted by implication or otherwise, and there is no representation or warranty that anything made in accordance with this marerial will be free from any patent or copyright infringement of a third party. this material or portions there of may contain techology or the subject relating to strategic products under the control of the forign exchange and foreign trade law of japan and may require an export license from the ministry of international trade and industry or other approval from another government agency. ?eiko epson corporation 2001, all rights reserved.
the information of the product number change configuration of product number comparison table between new and previous number starting april 1, 2001 the product number will be changed as listed below. to order from april 1, 2001 please use the new product number. for further information, please contact epson sales representative. devices s1 l 60843 f 00a0 packing specification specifications shape ( ? 2) model number model name ( ? 1) product classification (s1:semiconductor) 00 previous number new number sla35000 series S1L35000 series sla3504 s1l35043 sla3506 s1l35063 sla3509 s1l35093 sla3516 s1l35163 ? 1: model name ? 2: shape k standard cell l gate array x embedded array b assembled on board, cob, bga c plastic dip d bare chip f plastic qfp h ceramic dip l ceramic qfp m plastic sop r tab?fp t tape carrier (tab) 2 tsop (standard bent) 3 tsop (reverse bent)
contents gate array S1L35000 series epson i design guide S1L35000 series table of contents chapter 1 overview................................................................................................. 1 1.1 features of the S1L35000 series ................................................................................ 1 1.2 master structure of the S1L35000 series.................................................................... 1 1.3 electrical characteristics and specifications of the S1L35000 series......................... 2 1.4 overview of gate array development flow................................................................. 6 chapter 2 estimating gate density and selecting the master............................ 8 2.1 dividing up logic between chips................................................................................. 8 2.2 determining gate density............................................................................................ 8 2.3 estimating the number of input/output terminals....................................................... 8 2.4 selecting the master .................................................................................................... 8 2.5 estimating the bcs that can be used in circuits which include ram........................ 9 chapter 3 cautions and notes regarding circuit design................................. 10 3.1 inserting input/output buffers .................................................................................... 10 3.2 the use of differentiating circuits is forbidden ........................................................ 10 3.3 wired logic is forbidden ........................................................................................... 10 3.4 hazard countermeasures.......................................................................................... 11 3.5 fan-out constraints................................................................................................... 11 3.6 bus circuits............................................................................................................. ... 11 3.7 schematic capture guidelines .................................................................................. 12 3.8 clock tree synthesis ................................................................................................. 13 3.9 restrictions and constraints on vhdl/verilog-hdl netlist....................................... 17 3.9.1 common restrictions and constraints ............................................................................. 17 3.9.2 restrictions and constraints for verilog netlist................................................................. 17 3.9.3 restrictions and constraints on vhdl netlist .................................................................. 18 chapter 4 input/out buffer and their use .......................................................... 19 4.1 types of input/output buffer in the S1L35000 series ............................................... 19 4.1.1 selecting i/o buffer ................................................................................................... ........ 19 4.2 i/o buffer configurations with a single power supply............................................... 20 4.2.1 i/o buffer configurations with a single 5.0v power supply ............................................. 20 4.2.1.1 input buffer configurations with a single 5.0v power supply.................................. 20 4.2.1.2 output buffer configurations with a single 5.0v power supply............................... 20 4.2.1.3 bi-directional buffer configurations with a single 5.0v power supply..................... 23 4.2.2 i/o buffer configurations with a single 3.0/3.3 v power supply ...................................... 24 4.2.2.1 input buffer configurations with a single 3.0/3.3 v power supply........................... 24 4.2.2.2 output buffer configurations with a single 3.0/3.3v power supply......................... 25 4.2.2.3 bi-directional buffer configurations with a single 3.0/3.3 v power supply.............. 27 4.3 oscillation circuit ...................................................................................................... .30 4.3.1 oscillation circuit configurations ..................................................................................... .30 4.3.2 oscillator circuit considerations ...................................................................................... .30 chapter 5 ram ...................................................................................................... 32 5.1 features................................................................................................................. .... 32 5.2 ram configuration and simulation model selection ................................................. 32 5.3 ram size ................................................................................................................. .. 33 5.4 investigating ram placement on master slice .......................................................... 35 5.5 explanation of functions............................................................................................ 36 5.6 delay parameters ...................................................................................................... 38 5.7 timing charts............................................................................................................ .46
contents ii epson gate array S1L35000 series design guide 5.8 ram test method ......................................................................................................49 5.9 estimating ram current consumption ......................................................................49 5.10 ram symbols and how they are used ..................................................................49 chapter 6 circuit design taking testability into account ............................... 51 6.1 considerations regarding circuit initialization ..........................................................51 6.2 considerations regarding compressing the test patterns.......................................51 6.3 ram test circuit........................................................................................................5 2 6.3.1 ram test pattterns ..................................................................................................... ..... 53 6.4 function cell test circuits .........................................................................................58 6.4.1 test circuit structures ............................................................................................... ...... 58 6.4.2 test patterns .......................................................................................................... .......... 58 6.4.3 test circuit data ...................................................................................................... ......... 59 6.5 test circuit which simplifies ac and dc testing .....................................................60 chapter 7 propagation delay and timing .......................................................... 67 7.1 simple delay models .................................................................................................67 7.2 load due to input capacitance (load a)...................................................................68 7.3 load due to interconnect capacitance (load b).......................................................69 7.4 propagation delay calculations.................................................................................70 7.5 calculating output buffer delay.................................................................................72 7.6 sequential cell setup/hold time ...............................................................................72 7.7 chip internal skew.....................................................................................................75 chapter 8 test pattern generation ..................................................................... 76 8.1 testability considerations..........................................................................................76 8.2 waveform types........................................................................................................76 8.3 constraints on the types of test patterns.................................................................77 8.3.1 test period ............................................................................................................ ........... 77 8.3.2 input delay............................................................................................................ ............ 77 8.3.3 pulse width............................................................................................................ ........... 77 8.3.4 input waveform format .................................................................................................. .. 78 8.3.5 strobe ................................................................................................................. .............. 78 8.4 notes regarding dc testing .....................................................................................78 8.5 notes regarding the use of oscillation circuits ........................................................80 8.6 regarding ac testing................................................................................................81 8.6.1 constraints regarding measurement events ................................................................... 81 8.6.2 constraints on the measurement locations for ac testing ............................................. 82 8.6.3 constraints regarding the path delay which is tested................................................... 82 8.6.4 other constraints...................................................................................................... ........ 82 8.7 test pattern constraints for bi-directional terminals ................................................82 chapter 9 estimating the power consumption ................................................. 83 9.1 calculating the power consumption..........................................................................83 9.2 constraints on power consumption ..........................................................................86 chapter 10 pin layout considerations............................................................... 87 10.1 estimating the number of power supply terminals ................................................87 10.2 number of simultaneous operations and adding power supplies..........................87 10.3 cautions and notes regarding the layout of terminals .........................................89 10.3.1 fixed power supply pins............................................................................................... .89 10.3.2 cautions and notes regarding the pin layout............................................................... 89 10.3.3 examples of recommended pin connections ............................................................... 96
chapter 1: overview gate array S1L35000 series epson 1 design guide chapter 1 overview the S1L35000 series is a family of ultra high-speed vlsi cmos gate arrays utilizing a 0.6 micron "sea-of-gates" architecture. 1.1 features of the S1L35000 series ?integration a max. of 161,841 gates (2 input nand gate equivalent) ?operating speed internal gates:0.30 ns (5.0 v typ.), 0.4 ns (3.3 v typ.) (2-input power nand, f/o = 2, al = 2 mm) input buffer: 0.48 ns (5.0 v typ.), 0.63 ns (3.3 v typ.) (f/o = 2, al = 2 mm) output buffer: 2.08 ns (5.0 v typ.), 2.86 ns (3.3 v typ.) (c l = 50 pf) ?process cmos 0.6 ? al 3 interconnect layers ?i/f levels input/output ttl/cmos compatible ?input modes ttl, cmos, ttl schmitt, cmos schmitt pull-up and pull-down resistors can be equipped internally (2 types for each resistor value) ?output modes normal, 3-state, bi-directional ?output drive i ol = 1, 4, 8, 12 ma, selectable (at 5.0 v) i ol = 0.5, 2, 4, 6 ma, selectable (at 3.3v) ?ram asynchronous 1-port, asynchronous 2-port 1.2 master structure of the S1L35000 series the S1L35000 series comprises 4 types of masters, from which the customer is able to select the master most suitable. table 1-1 overview of the S1L35000 series note: *1: this is the value when there are no cells, such as ram cells. the cell use effciency is dependent not only on the scope of the circuits, but also on the number of signals, the number of branches per signal, etc.; thus, use the values in this table only as an estimate. master bc total number of pads number of columns (x) number of rows (y) cell use ratio (u) *1 s1l35043 41417 110 499 83 65% s1l35063 64320 130 480 134 60% s1l35093 95760 162 570 168 55% s1l35163 161841 210 739 219 50%
chapter 1: overview 2 epson gate array S1L35000 series design guide 1.3 electrical characteristics and speci?ations of the S1L35000 series table 1-2 S1L35000 absolute max. ratings (v ss = 0 v) table 1-3 recommended operating conditions for the S1L35000 series (for single power supplies) item symbol limits unit power supply voltage v dd -0.3 to 6.0 v input voltage v i -0.3 to v dd + 0.5 v output voltage v o -0.3 to v dd + 0.5 v output current/pin i out ?25 ma storage temperature t stg -65 to 150 o c item symbol min. ty p. max. unit power supply voltage v dd 2.70 3.00 4.75 4.50 3.00 3.30 5.00 5.00 3.30 3.60 5.25 5.50 v input voltage v i v ss -- v dd v operating temperature topr 0 -40 25 25 70 85 o c o c normal input rising time t ri -- -- 50 ns normal input falling time t fa -- -- 50 ns schmitt input rising time t ri -- -- 5 ms schmitt input falling time t fa -- -- 5 ms
chapter 1: overview gate array S1L35000 series epson 3 design guide table 1-4 electrical characteristics of the S1L35000 series (v dd = 5 v, v ss = 0 v, ta = -40 to 85 o c) item symbol conditions min. ty p. max. unit quiescent current i dds quiescent conditions -- -- 400 ? input leakage current i li -- -1 -- 1 a off state leakage current i oz -- -1 -- 1 a high level output voltage v oh i oh = -1 ma (type m), -4 ma (type 1) -8 ma (type 2), -12 ma (type 3) v dd = min. v dd -0.4 -- -- v low level output voltage v ol i ol = 1 ma (type m), 4 ma (type 1), 8 ma (type 2), 12 ma (type 3) v dd = min. -- -- 0.4 v high level input voltage v ih1 cmos level, v dd = max. 3.5 -- -- v low level input voltage v il1 cmos level, v dd = min. -- -- 1.0 v high level input voltage v t1+ cmos schmitt, v dd = 5.0 v -- -- 4.0 v low level input voltage v t1- cmos schmitt, v dd = 5.0 v 0.8 -- -- v hysteresis voltage v h1 cmos schmitt, v dd = 5.0 v 0.3 -- -- v high level input voltage v ih2 ttl level, v dd = max. 2.0 -- -- v low level input voltage v il2 ttl level, v dd = min. -- -- 0.8 v high level input voltage v t2+ ttl schmitt, v dd = 5.0 v -- -- 2.4 v low level input voltage v t2- ttl schmitt, v dd = 5.0 v 0.6 -- -- v hysteresis voltage v h2 ttl schmitt, v dd = 5.0 v 0.1 -- -- v pull-up resistance r pu v i = 0 v type 1 25 50 100 k ? type 2 50 100 200 pull-down resistance r pd v i = v dd type 1 25 50 100 k ? type 2 50 100 200 input terminal capacitance c i f = 1 mhz , v dd = 0 v -- -- 12 pf output terminal capacitance c o f = 1 mhz, v dd = 0 v -- -- 12 pf input/output terminal capacitance c io f = 1 mhz, v dd = 0 v -- -- 12 pf
chapter 1: overview 4 epson gate array S1L35000 series design guide table 1-5 electrical characteristics of the S1L35000 series (v dd = 3 v ?0.3 v, v ss = 0 v, ta = -40 to 85 o c) item symbol conditions min. ty p. max. unit quiescent current i dds quiescent conditions -- -- 260 ? input leakage current i li -- -1 -- 1 a off state leakage current i oz -- -1 -- 1 a high level output voltage v oh i oh = -0.5 ma (type m), -1.8 ma (type 1) -3.5 ma (type 2) , -5 ma (type 3) v dd = min. v dd -0.3 -- -- v low level output voltage v ol i ol = 0.5 ma (type m), 1.8 ma (type 1) , 3.5 ma (type 2) , 5 ma (type 3) v dd = min. -- -- 0.3 v high level input voltage v ih1 cmos level, v dd = max. 2.0 -- -- v low level input voltage v il1 cmos level, v dd = min. -- -- 0.8 v high level input voltage v t1+ cmos schmitt, v dd = 3.0 v -- -- 2.3 v low level input voltage v t1- cmos schmitt, v dd = 3.0 v 0.5 -- -- v hysteresis voltage v h1 cmos schmitt, v dd = 3.0 v 0.1 -- -- v pull-up resistance r pu v i = 0 v type 1 50 100 200 k ? type 2 100 200 400 pull-down resistance r pd v o = v dd type 1 50 100 200 k ? type 2 100 200 400 input terminal capacitance c i f = 1 mhz, v dd = 0 v -- -- 12 pf output terminal capacitance c o f = 1 mhz, v dd = 0 v -- -- 12 pf input/output terminal capacitance c io f = 1 mhz, v dd = 0 v -- -- 12 pf
chapter 1: overview gate array S1L35000 series epson 5 design guide table 1-6 electrical characteristics of the S1L35000 series (v dd = 3.3 v ?0.3 v, v ss = 0 v, ta = -40 to 85 o c) item symbol conditions min. ty p. max. unit quiescent current i dds quiescent conditions -- -- 290 ? input leakage current i li -- -1 -- 1 a off state leakage current i oz -- -1 -- 1 a high level output voltage v oh i oh = -0.5 ma (type m), -2 ma (type 1) , -4 ma (type 2) , -6 ma (type 3) v dd = min. v dd -0.3 -- -- v low level output voltage v ol i ol = 0.5 ma (type m), 2 ma (type 1) , 4 ma (type 2) , 6 ma (type 3) v dd = min. -- -- 0.3 v high level input voltage v ih1 cmos level, v dd = max. 2.2 -- -- v low level input voltage v il1 cmos level, v dd = min. -- -- 0.8 v high level input voltage v t1+ cmos schmitt, v dd = 3.3 v -- -- 2.4 v low level input voltage v t1- cmos schmitt, v dd = 3.3 v 0.6 -- -- v hysteresis voltage v h1 cmos schmitt, v dd = 3.3 v 0.1 -- -- v pull-up resistance r pu v i = 0 v type 1 45 90 180 k ? type 2 90 180 360 pull-down resistance r pd v i = v dd type 1 45 90 180 k ? type 2 90 180 360 input terminal capacitance c l f = 1 mhz, v dd = 0 v -- -- 12 pf output terminal capacitance c o f = 1 mhz, v dd = 0 v -- -- 12 pf input/output terminal capacitance c io f = 1 mhz, v dd = 0 v -- -- 12 pf
chapter 1: overview 6 epson gate array S1L35000 series design guide 1.4 overview of gate array development flow gate arrays are developed jointly by the customer and epson. system design, circuit design, and test pattern design is performed by the customer, based on various reference materials, including the cell libraries provided to the customer by epson. various modes of interface, listed below, are possible between the customer and epson during design, depending on the stage in gate array development wherein the customer interfaces with epson. when interfacing with epson, the customer is to provide the necessary data and documents to epson. the customer performs schematic capture, logic synthesis and simulation using eda software and auklet* supported by epson. place and route is performed by epson. both the customer and epson are responsible for ?al sign-off simulations. note) * : auklet is the epson's asic desgin support system that can run on a personal computer- os : ms-windows 95/98, nt platform. the simulation is currently supported by the following eda software: ?verilog-xl (*1) ?vss (*2) ?modelsim (*3) note) *1 : verilog-xl is a registered trademark of cadence desgin systems corporation, usa. *2 : vss is a registered trademark of synopsys inc., usa. *3 : modelsim is a registered trademark of model technology corp., usa. for more information, refer to the gate array technical guide or contact to our sales of?e for technical support.
chapter 1: overview gate array S1L35000 series epson 7 design guide the process ?w of the gate array development process is shown below: note: when the customer performs all tasks to the point of logical simulations and delay simulations on engineering workstations, etc., the route taken is (2). when epson performs the logical simulations, the route taken is (1). customer distributor (interface) epson product plan circuit design logical check verification schematic pin assinment * timing wave form * marking diagram logical check verification* timing check verification * place & rout post simulation * test pattern (timing chart) g/a development request schematic pin assinment timing wave form marking diagram p/o * p/o simulation list customer spec (sign off) verification make masks ts (test sample) fabrication es (engineering sample) fabrication mp setup delivery spec. publication mp delivery spec delivery spec approval approve delivery spec g/a development request (simulation) (simulation) (simulation) test pattern design functional spec. ng ews ok ng ok ok ng ok ng ng ng check check 1 2 ( ) is based on customers requirement. * jobs are done by customer and epson engineer. simulation file es(ts) prototype approval es(ts) approve the prototype ok ok
chapter 2: estimating gate density and selecting the master 8 epson gate array S1L35000 series design guide chapter 2 estimating gate density and selecting the master methods and guidelines are described below to assist in de?ing the logic which will be integrated into a gate array, estimating the array requirements, and determining the appropriate master for a given application. 2.1 dividing up logic between chips when extracting logic, which is to be integrated into gate arrays from the system being created by the user, the logic should be selected with the following criteria in mind. ?integration criteria (1) quantity of logic to integrate (2) quantity of input, output and bi-directional signals required (3) package to be used (4) power consumption generally, the larger the gate density, the more power is consumed, and the more input and output terminals required. because of this, it may be better, from the perspective of total cost or from the perspective of power consumption, etc., to divide the circuit into multiple chips, rather than forcing them into a single chip. 2.2 determining gate density in the case of gate arrays, the scope of the array is de?ed as the sum of gates or basic cells (bcs) used. one gate or basic cell is typically de?ed as being equivalent to one two-input nand gate (or four transistors). the "gate array S1L35000 series msi cell library" can be used as reference to facilitate gate count estimation. 2.3 estimating the number of input/output terminals de?ing the number of i/o signals, test signals and power pins required for a given application has a bearing on the array member suitable for that application. the appropriate number of i/o pads must be available on the array member to satisfy the application signal requirements. estimate the number of power supply pins using the method discussed in chapter 10. 2.4 selecting the master select the appropriate master from the cmos device catalog S1L35000 series tables, based on the estimated number of bcs, the number of required input and output pins (including power supply pins) and the package to be used. the actual number of bcs (bc a ) which can be used for each device type is estimated using the following formula from the gross number of bcs (bc g ) loaded on each master (shown in table 1-1 of the previous chapter) and the cell utilization ratio (u). bc a = u x bc g
chapter 2: estimating gate density and selecting the master gate array S1L35000 series epson 9 design guide where u = 0.50 to 0.65 note: when a ram circuit is included, this estimate should be made after refering to the following section and after refering to chapter 5. 2.5 estimating the bcs that can be used in circuits which include ram ram blocks, in comparison to msi cells, are extremely large and have ?ed shapes (de?ed vertical and horizontal dimensions). because of this, some ram blocks which may appear to ? on the chip because of calculations based on the number of bcs may, in actuality, not be placable on a given master. thus, the ?st decision is that of whether or not the ram con?uration is available on a given master. please refer to chapter 5. once the masters which can accommodate the ram have been selected, it becomes possible to estimate the number of bcs (bc awr ) of random logic (excluding ram) available using the formula below. bc awr = 0.9 x u x (bc g - bc ram ) where bc awr is the number of bcs available for random logic bc g is the gross bcs available on a mater (raw gates) bc ram is the bc use of ram(s) (see chapter 5 for bc calculation) u is the utilization ratio note: actual bcs available (bc awr ) is design dependent. use the formula above for estimation purposes only. please consult epson for design speci? information.
chapter 3: cautions and notes regarding circuit design 10 epson gate array S1L35000 series design guide chapter 3 cautions and notes regarding circuit design 3.1 inserting input/output buffers when designing your circuit using gate arrays, always be sure to use input/output buffers to exchange signals with external devices. due to cmos ic's extreme vulnerability to electrical static discharge (esd), protection circuitry has been incorporated within the input/output buffers. in addition, due to limitations on chip layout, be sure to insert input or output buffers between external terminals and internal cells. 3.2 the use of differentiating circuits is forbidden in lsis, the propagation delay (tpd) of each gate varies depending on process variance during mass production and on the operating environment. therefore, depending on the process dispersions and operating conditions, differentiating circuits using the relative time difference of tpd, like the one shown in figure 3-1, may not be able to obtain a suf?ient pulse width, causing the circuit to operate erratically. when using a differentiating circuit, be sure to use one that utilizes ?p-?ps, and not the one shown in figure 3-1. figure 3-1 example of a differentiating circuit 3.3 wired logic is forbidden because the S1L35000 uses cmos transistors, wired logic as in bipolar transistors cannot be con?ured. consequently, cell output terminals cannot be wired together, as shown in figure 3-2. it is only in a bus-circuit con?uration that output terminals can be connected together. figure 3-2 example of forbidden wired logic
chapter 3: cautions and notes regarding circuit design gate array S1L35000 series epson 11 design guide 3.4 hazard countermeasures in circuits or decoder cells con?ured by combining gates such as nand or nor gates, an extremely short pulse may be generated due to the difference in delay times between gates. this short pulse is known as a "hazard" and, when fed into the clock or reset terminals of ?p-?ps, causes malfunction. therefore, circuits in which such a hazard is likely to occur must be con?ured so as to prevent the hazard from propagating. alternately, for decoders, it may be necessary to use one that has an enable terminal. 3.5 fan-out constraints the tpd of a logic gate is determined by the load capacitance of its output terminal. an excessively large load capacitance may not only cause the tpd to become large, but may also cause malfunction. therefore, the output terminals of each logic gate are subject to limitations on the number of loads that can be connected. these are known as "fan-out constraints." the input-terminal capacitance of each logic gate, on the other hand, tends to differ for each logic-gate input. the input capacitance of each logic gate, as referenced to the input capacitance of an inverter (ini) = 1, is known as the "fan-in." in the design of your circuit, con?m that the sum total of fan-ins connected to the output terminals of each logic gate will not exceed the fan-out constraints of those output terminals. furthermore, for logic gates operating at high speed such as high-speed clock lines (fmax = 40 mhz or more), con?m that the output-terminal capacitance of those gates is approximately half of the fan-out constraints. 3.6 bus circuits a bus circuit is con?ured with 3-state logic circuits, so that one of the outputs connected to the bus is driven active (while the other outputs are placed in the high-impedance state) by turning the bus control signals on or off. in this way, one transmission signal line on the bus is shared by dividing its use time. although bus circuits are very effective for logic design, note the following when using a bus circuit. notes regarding the use of bus circuits (1) bus cells can only be used for bus circuits (for the S1L35000 series bus cells, see table 3-1). (2) when using bus cells, add bus de?ition cells blt to the bus when con?uring your circuit. (3) up to 32 bus cells can be connected to one length of bus. (4) of the bus cells connected to one length of bus, only one output can be active (0 or 1) at one time, and all other bus-cell outputs must be placed in the high-impedance state (z). (5) even when all of the bus cells connected to one length of bus are in the high-impedance state (z), data may be retained by a bus latch cell. however, leave the retained data ?ating, and do not use it as a logic signal.
chapter 3: cautions and notes regarding circuit design 12 epson gate array S1L35000 series design guide (6) in the creation of your test pattern, make sure the bus's initial state will be easily settled to provide improved testability. in addition, add one or more test terminals to make the bus easily controllable. (7) the bus control signals within the same event rate can be switched only once. (8) an excessive fan-out of the bus circuit may cause the propagation delay time to increase, making high-speed operation dif?ult. the usable bus cells in the S1L35000 series are listed in table 3-1. table 3-1 table of S1L35000 series bus cells figure 3-3 typical con?uration of a bus cell circuit 3.7 schematic capture guidelines please adhere to the following conventions when designing an asic via manual schematic entry: ? use logic cells found in gate array S1L35000 series msi cell library. ? use orthogonal (not oblique) connections when wiring logic cells to one another. ? primary uni-directional i/o and bi-directional i/o signal names must be 2 to 32 characters in length, and must begin with an alphabetic character. cell type cell name 1 bit 4 bit 8 bit bus latches xblt 1 xblt 4 xblt 8 bus drier xtsb, xtsbp xt244h xt244 inverting bus driver xtsv, xtsvp xt240h xt240 transparent latches with reset and 3-state output xt373h xt373 d-?p ?ps with rest and 3-state output xt374h xt374 1-bit ram xrm1 blt tsb tsb in 1 na 2
chapter 3: cautions and notes regarding circuit design gate array S1L35000 series epson 13 design guide 3.8 clock tree synthesis (1) overview clock tree synthesis is a support that automatically inserts the clocktree into the buffer group that optimizes the skew and delay time of ?lock line? if a customer has a program to insert clocktree to adjust the fan-out of ?lockline? clock skew may be large, so the p & r tool is started and the placing and routing for designing the gate array are executed voluntarily. also, the propagation delay time may be longer than estimated because there are many cases it is dif?ult to maintain a good balance between the wire interconnecting load and the intrinsic cell delay. the clock tree synthesis is used to solve this problem. refer to the actual results to use the clock tree synthesis as follows: (2) how to examine the clock tree synthesis when the clock tree is inserted automatically, the customer must insert the special buffer to the clock line for the following three purposes. ? judging the place to insert the clock tree synthesis. ? estimating the delay time of the clock tree inserted and execute the simulation of virtual wire interconnecting level (pre-simulation). back annotate the delay time of the inserted clock tree to accurately estimate the post- simulation. select the special buffer for the clock tree synthesis in the table of special buffers mentioned later.then insert the special buffer selected from the table into the clock line taking into consideration the restriction or notes mentioned later and the same placing as the normal cells. otherwise, if the logic are designed by hdl, as the special buffer can not insert automatically the clock line, assign directly the hdl of the content using the script language. note that another buffer is not combined in the clock line inserted in the special buffer, and execute the following command: set_dont_touch_net net_name
chapter 3: cautions and notes regarding circuit design 14 epson gate array S1L35000 series design guide [the special buffer] select the special buffer from the table below corresponding to the estimated number of fan-outs. note 1: the value ??(load delay of fan-out) of these cells is set ??at the pre-simulation. note 2: the number of fan-outs of these cells is set to the infinity. note 3: please consider that the load delay for the number of fan-outs is not accurately and only estimated. s1l9000f, s1l30000, s1l50000 series cell name to max. (ns) estimated number of fan-out crbf2 2.00 0 to 500 crbf3 3.00 500 to 3000 crbf4 4.00 3000 to 10000 crbf5 5.00 over 10000 crbf6 6.00 crbf7 7.00 crbf8 8.0 S1L35000 series cell name to max. (ns) estimated number of fan-out xcrbf2 2.00 0 to 500 xcrbf3 3.00 500 to 3000 xcrbf4 4.00 3000 to 10000 xcrbf5 5.00 over 10000 xcrbf6 6.00 xcrbf7 7.00 xcrbf8 8.0
chapter 3: cautions and notes regarding circuit design gate array S1L35000 series epson 15 design guide [restriction and notes] ? target series: s1l9000f, s1l30000, S1L35000, s1l50000 ? the special buffer can not be used for any purpose other than the clock tree synthesis. ? the clock tree synthesis can also be used for data line and other control signals. however, when the nets used in the synthesis are increased, the skew and propagation delay also became larger. therefore, the number of nets to be used in the synthesis is less than 10 and the net which has a critical and large fan-out should be used. if a net which has a small fan-out is used for the clock tree synthesis, the propagation delay and skew may be larger. the target net with fan-out should be used more than scores. ? as there are cases corresponding to the skew adjustment between multiple clock lines, contact epson for handing in the detail schematic (the clock line con?uration is described very clearly) to be checked. ? for the clock group separated into multiple clock lines with the same root of clock by the gates, contact epson to obtain the materials of ?ated clock tree synthesis explanations? [necessary information from a customer] send the following information until the data is released, because the clock tree synthesis is used ef?iently. note 1: the target values on the table are needed to estimate to use the synthesis. the target values are not always satisfied. note 2: if there is no target values, write the comments for each item in the table. example: as smaller as possible instance name of crbf* target skew value target propagation delay (min./max.)
chapter 3: cautions and notes regarding circuit design 16 epson gate array S1L35000 series design guide [imaging schematic] the schematic created by a customer and the layout schematic after executing the clock tree synthesis in epson are shown as follows: figure 3-5 layout schematic after executing the clock tree synthesis in epson clock root combining with the clockt ree back annotation of propagation delay crbf* figure 3-4 a customers schematic
chapter 3: cautions and notes regarding circuit design gate array S1L35000 series epson 17 design guide 3.9 restrictions and constraints on vhdl/verilog-hdl netlist the vhdl/verilog-hdl net list to be interfaced to epson shall be a pure gate-level net list (not containing description of operation). the restrictions and constraints in developing epson asic using vhdl/verilog hdl are as follows. 3.9.1 common restrictions and constraints (1) names of external terminal (i/o terminal) use only upper-case letters. number of characters: 2 to 32 usable characters : alphanumeric characters and ?. use an alphabetical letter at the head. examples of prohibited character strings : 2 input : a digit is at the head. \2input : ??is at the head. inputa : lower-case letters are included. _inputa : ??is at the head. tna[3:0] : a bus is used for the name of the external terminal. ina[3] : a bus is used for the name of the external terminal. (2) names of internal terminal (including bus net names) upper-and lower-case letters can be used in combination, except the following. combinations of the same words expressed in upper-and lower-case letters, such as ?reset_?and ?reset_.? number of characters : 2 to 32 usable characters :alphanumeric characters, ?,??[ ]_?(verilog bus blanket), and _()_ (vhdl bus blanket) with an alphabetical letter at the head. (3) bus description is prohibited at the most signi?ant place of the module. examples: data [0:3], data [3], and data [2] are prohibited.data0, data1, and data2 are all allowed. (4) you can use i/o cells of the same library series, but cannot combine those of different series. (5) it is not possible to describe operations in behaviors or in the c language. such descriptions existing in the net list are invalid. (6) precision of the time scale of the library of each series is 1 ps. 3.9.2 restrictions and constraints for verilog netlist (7) descriptions using the functions ?ssign?and ?ran?are prohibited in the gate-level verilog net list. (8) descriptions of connection with cell pin names are recommended in the verilog net list. example: connection with pin names: in2 inst_1 (.a(inst_2),.x(inst_3)); recommended connection with net names: in2 inst_1(net1, net2):
chapter 3: cautions and notes regarding circuit design 18 epson gate array S1L35000 series design guide (9) you cannot use the verilog command ?orce?as a description of ?p-?p operation. (example: force logic .singal = 0;) (10) the time scale description is added at the head of the gate-level net list generated by the synopsys design compiler. set it at the value described in the epson verilog library. see (6) for the time scale of each series. example: 'timescale 1ps/1ps (11) epson prohibits combination of a bus single port name and a name that includes ?\_? such as the following, in the same module. input a [0]; wire \a [0]; (12) the following letter strings are reserved for verilog, which cannot be used as a user-de?ed name. always, and, assign, begin, buf, bu?0, bu?1, case, design,default, defparam, disable, else, end, endcase, endfunction, endmodule, endtask, event, for, force, forever, fork, function, highz0, highz1, if, initial, inout, input, integer, join, large, medium, module, nand, negedge, nor, not, notif0, notif1, or, output, parameter, posedge, pull0, pull1, reg, release, repeat, scalared, small, specify, strong0, strong1, supply0, supply1, task, time, tri, tri0, tri1, trinand, trior, trireg, vectored, wait, wand, weak0, weak1, while, wire, wor, xor, xnor 3.9.3 restrictions and constraints on vhdl netlist (13) in addition to the constraints in (1), the following letter strings are also prohibited. inputa_ : ??is used at the end. input_ _a : ??is used twice or more in succession. read : used in the system. write : used in the system. (14) the following letter strings are reserved for vhdl, which cannot be used as a user-de?ed name. abs, access, after, alias, all, and, architecture, array, assert, attribute, begin, block, body, buffer, bus, case, component, con?uration, constant, disconnect, downto, else, elsif, end, entity, exit, ?e, for, function, generate, generic, guarded, if, in, inout, is, label, library, linkage, loop, map, mod, nand, new, next, nor, not, null, of, on, open, or, others, out, package, port, procedure, process, range, record, register, rem, report, return, select, severity, signal, subtype, then, to, transport, type, units, until, use, variable, wait, when, while, with, xor (15) to use epson utilities and tools, it is necessary to change the vhdl format into the verilog format. therefore, the letter strings reserved for verilog in (12) are also prohibited.
chapter 4: input/out buffer and their use gate array S1L35000 series epson 19 design guide chapter 4 input/out buffer and their use 4.1 types of input/output buffer in the S1L35000 series various i/o buffers types of the S1L35000 series are available according to the input inter- face level, output drive capacity, use or no use of pull-up and pull-down resistors, and the pull-up and pull-down resistors. you can select the ones appropriate to your needs. 4.1.1 selecting i/o buffer the S1L35000 series provides a wide range of input / output buffers.you can select buffer parameters, including input interface level, schmitt trigger input or not, output drive capabil-ity and a pull-up or pull-down resistance. this allows you to select the most suitable buffer for each application.b) is a schmitt trigger input necessary? (are hysteresis characteristics necessary?) (1) selecting the input cell a) is the required interface level a cmos level or a ttl level? b) is a schmitt trigger input necessary? (are hysteresis characteristics necessary?) c) is it necessary to add pull-up/pull-down resistors? (2) selecting the output cell a) how much output current must be driven?(i ol / i oh ) b) are noise countermeasures necessary? (3) selecting bi-directional cells select the bi-directional cells by examining both sets of criteria for selecting the input cells and selecting the output cells. ?i/o interface level 1) 5.0v system single power supply input level ttl level, cmos level, ttl schmitt, cmos schmitt output level cmos level 2) 3.0 v system single power supply input level ttl schmitt, cmos schmitt output level cmos level note 1 :the 3.0 v/ 3.3 v system cmos level is about the same value as the 5.0v system ttl level. when a single 3.0 / 3.3 v power supply is used, ttl level input cannot be used. ?output drive capability see the electrical characteristics (tables 1.4 to 1.6). ?pull-up/pull-down resistance see the electrical characteristics (tables 1.4 to 1.6).
chapter 4: input/out buffer and their use 20 epson gate array S1L35000 series design guide some i/o buffers of the S1L35000 series need to use a combination of i/o cells and internal interface cells. the input buffer, output buffer, and bi-directional buffer con?uration for single power supplies are expained in detail biginning with section 4.2. 4.2 i/o buffer con?urations with a single power supply when using a single power supply, the power supply voltage (v dd ) may be either 5.0v, 3.3v or 3.0v. also, i/o buffer can be used either 5.0v, 3.3v or 3.0v. i/o buffer con?urations with a single power supply either 3.0v or 5.0v are explained below. 4.2.1 i/o buffer con?urations with a single 5.0v power supply 4.2.1.1 input buffer con?urations with a single 5.0v power supply the input buffer function is structured of input cells only. table 4-1 input cell (combinations of i/o cells) note: when ? value is 1 or 2, pull-up/pull-down resistance values correspond to 1:50 k ? ., 2:100 k ? respectively. 4.2.1.2 output buffer con?urations with a single 5.0v power supply please con?ure the output buffers using pre-drivers (such as xpdv1t, xpdv1at, xpdv1bt, xpdv2t, xpdv2at, xpdv2bt, etc.), and output cells (such as xuom to xuo3). see figure 4-1 for connectivity and reference table 4-2 below regarding the pre-driver and output cell combinations. cell name input level function pull-up/pull-down resistance xibt xibtp ? xibtd ? ttl ttl ttl buffer buffer buffer none pull-up resistance (50 k ? , 100 k ? ) pull-down resistance (50 k ? , 100 k ? ) xibc xibcp ? xibcd ? cmos cmos cmos buffer buffer buffer none pull-up resistance (50 k ? , 100 k ? ) pull-down resistance (50 k ? , 100 k ? ) xibs xibsp ? xibsd ? ttl schmitt ttl schmitt ttl schmitt buffer buffer buffer none pull-up resistance (50 k ? , 100 k ? ) pull-down resistance (50 k ? , 100 k ? ) xibh xibhp ? xibhd ? cmos schmitt cmos schmitt cmos schmitt buffer buffer buffer none pull-up resistance (50 k ? , 100 k ? ) pull-down resistance (50 k ? , 100 k ? )
chapter 4: input/out buffer and their use gate array S1L35000 series epson 21 design guide figure 4-1 examples of pre-driver and output cell con?urations table 4-2 combinations of pre-drivers and output cells notes: * v ol = 0.4 v (v dd = 5.0 v) ** v oh = v dd - 0.4 v (v dd = 5.0 v) *** in addition to the con?urations in table 4-2, the output buffers may be con?ured with pre-drivers which do not have test terminals. customers desiring to use such structures should direct inquiries to epson. function i ol * / i oh ** cell structure*** normal output for low noise 1ma/-1ma 4ma/-4ma 8ma/-8ma 12ma/-12ma xuom+xpdv1t xuo1+xpdv1t xuo2+xpdv1t xuo3+xpdv1t normal output for high speed 1ma/-1ma 4ma/-4ma 8ma/-8ma 12ma/-12ma xuom+xpdv1at xuo1+xpdv1at xuo2+xpdv1at xuo3+xpdv1at normal output with slew rate control 1ma/-1ma 4ma/-4ma 8ma/-8ma 12ma/-12ma xuom+xpdv1bt xuo1+xpdv1bt xuo2+xpdv1bt xuo3+xpdv1bt normal output with slew rate control for falling edge only 12ma/-12ma xuo3l+xpdv3t 3-state output for low noise 1ma/-1ma 4ma/-4ma 8ma/-8ma 12ma/-12ma xuom+xpdv2t xuo1+xpdv2t xuo2+xpdv2t xuo3+xpdv2t 3-state output for high speed 1ma/-1ma 4ma/-4ma 8ma/-8ma 12ma/-12ma xuom+xpdv2at xuo1+xpdv2at xuo2+xpdv2at xuo3+xpdv2at 3-state output with low slew rate control 1ma/-1ma 4ma/-4ma 8ma/-8ma 12ma/-12ma xuom+xpdv2bt xuo1+xpdv2bt xuo2+xpdv2bt xuo3+xpdv2bt 3-state output with slew rate control for falling edge only 12ma/-12ma xuo3l+xpdv4t xuo1 a e td te ts p n output enable for test a td ts p n output for test signal output signal xpdv2t xpdv1t (b) xuo1 + xpdv2t = 3 - state output (a) xuo1 + xpdv1t = normal output xuo1 output
chapter 4: input/out buffer and their use 22 epson gate array S1L35000 series design guide as is shown in table 4-2, the combination with xuo3l and xpdv3t can be output more than normal slew rate for falling edge only . also, both xpdv1bt and xpdv2bt are output more than normal slew rate for falling and rising edges. usually, they are used in combination with xuo3. ?xodn (open drain output cell) usage as is shown in table 4-3, con?ure open drain output functionality using the xodnx output cell and pre-driver combinations with the n terminal connection only. do not connect the p terminal of the pre-driver output. (see figure 4-2) figure 4-2 example of xodn con?uration table 4-3 combinations of pre-drivers and xodn cell usage notes: * v ol = 0.4 v (v dd = 5 v) ** in addition to the con?urations on table 4-3, the output buffers may be con?ured with pre-drivers which do not have test terminals. customers desiring to use such structures should direct inquiries to epson. function i ol * cell structure** normal output for low noise 1ma 4ma 8ma 12ma xodnm+xpdv1t xodn1+xpdv1t xodn2+xpdv1t xodn3+xpdv1t normal output for high speed 1ma 4ma 8ma 12ma xodnm+xpdv1at xodn1+xpdv1at xodn2+xpdv1at xodn3+xpdv1at normal output with slew rate control 12ma xodn3l+xpdv3t a td ts p n output for test output signal xpdv1t (xodn1 + xpdv1t = n-ch open drain) xodn1
chapter 4: input/out buffer and their use gate array S1L35000 series epson 23 design guide 4.2.1.3 bi-directional buffer con?urations with a single 5.0v power supply bi-directional buffers are con?ured from combinations of pre-drivers (with enable terminals) and bi-directional cells. (see figure 4-3.) figure 4-3 examples of pre-driver and bi-directional cell con?urations table 4-4 combinations of pre-drivers and bi-directional cells (1/2) input level function i ol */i oh ** cell structure*** ttl bi-directional for low noise output 1ma/-1ma 4ma/-4ma 8ma/-8ma 12ma/-12ma xutm+xpdv2t xut1+xpdv2t xut2+xpdv2t xut3+xpdv2t ttl bi-directional for high speed output 1ma/-1ma 4ma/-4ma 8ma/-8ma 12ma/-12ma xutm+xpdv2at xut1+xpdv2at xut2+xpdv2at xut3+xpdv2at ttl bi-directional with low slew rate control output 1ma/-1ma 4ma/-4ma 8ma/-8ma 12ma/-12ma xutm+xpdv2bt xut1+xpdv2bt xut2+xpdv2bt xut3+xpdv2bt ttl bi-directional with slew rate control output for falling edge only 12ma/-12ma xut3l+xpdv4t cmos bi-directional for low noise output 1ma/-1ma 4ma/-4ma 8ma/-8ma 12ma/-12ma xucm+xpdv2t xuc1+xpdv2t xuc2+xpdv2t xuc3+xpdv2t cmos bi-directional for high speed output 1ma/-1ma 4ma/-4ma 8ma/-8ma 12ma/-12ma xucm+xpdv2at xuc1+xpdv2at xuc2+xpdv2at xuc3+xpdv2at cmos bi-directional with low slew rate control output 1ma/-1ma 4ma/-4ma 8ma/-8ma 12ma/-12ma xucm+xpdv2bt xuc1+xpdv2bt xuc2+xpdv2bt xuc3+xpdv2bt cmos bi-directional with slew rate control output for falling edge only 12ma/-12ma xuc3l+xpdv4t xut1 a e td te ts p n bidirec- input signal output enable for test signal xpdv2t (a) xut1 + xpdv2t = bi-directional tional (b) xut3l + xpdv4t = bi-directional with slew rate xut3l a e td te ts p n1 bidirectional input signal output enable for test signal xpdv4t n2
chapter 4: input/out buffer and their use 24 epson gate array S1L35000 series design guide table 4-4 combinations of pre-drivers and bi-directional cells (2/2) notes: * v ol = 0.4 v (v dd = 5.0 v) ** v oh = v dd - 0.4 v (v dd = 5.0 v) *** in addition to the con?urations in table 4-4, bi-directional buffers may be con?ured with pre-drivers which do not have test terminals. most bi-directional buffers have two types of pull-up resistance options and two types of pull-down resistance options. customers desiring such should direct inquiries to epson. 4.2.2 i/o buffer con?urations with a single 3.0/3.3 v power supply 4.2.2.1 input buffer con?urations with a single 3.0/3.3 v power supply table 4-5 input cells notes:when ? value is 1 or 2, pull-up/pull-down resistance values correspond to 1:90 k ? ., 2:180 k ? respectively. ** in a 3.0 v/3.3 v single power supply ttl level input cannot be used. input level function i ol */i oh ** cell structure ttl schmitt bi-directional for low noise output 1ma/-1ma 4ma/-4ma 8ma/-8ma 12ma/-12ma xusm+xpdv2t xus1+xpdv2t xus2+xpdv2t xus3+xpdv2t ttl schmitt bi-directional for high speed output 1ma/-1ma 4ma/-4ma 8ma/-8ma 12ma/-12ma xusm+xpdv2at xus1+xpdv2at xus2+xpdv2at xus3+xpdv2at ttl schmitt bi-directional with low slew rate control output 1ma/-1ma 4ma/-4ma 8ma/-8ma 12ma/-12ma xusm+xpdv2bt xus1+xpdv2bt xus2+xpdv2bt xus3+xpdv2bt ttl schmitt bi-directional with slew rate control output for falling edge only 12ma/-12ma xus3l+xpdv4t cmos schmitt bi-directional for low noise output 1ma/-1ma 4ma/-4ma 8ma/-8ma 12ma/-12ma xuhm+xpdv2t xuh1+xpdv2t xuh2+xpdv2t xuh3+xpdv2t cmos schmitt bi-directional for high speed output 1ma/-1ma 4ma/-4ma 8ma/-8ma 12ma/-12ma xuhm+xpdv2at xuh1+xpdv2at xuh2+xpdv2at xuh3+xpdv2at cmos schmitt bi-directional with low slew rate control output 1ma/-1ma 4ma/-4ma 8ma/-8ma 12ma/-12ma xuhm+xpdv2bt xuh1+xpdv2bt xuh2+xpdv2bt xuh3+xpdv2bt cmos schmitt bi-directional with slew rate control output for falling edge only 12ma/-12ma xuh3l+xpdv4t cell name input level** function pull-up/pull-down resistance xibc xibcp ? xibcd ? cmos cmos cmos buffer buffer buffer none pull-up resistance (90 k ? , 180 k ? ) pull-down resistance (90 k ? , 180 k ? ) xibh xibhp ? xibhd ? cmos schmitt cmos schmitt cmos schmitt buffer buffer buffer none pull-up resistance (90 k ? , 180 k ? ) pull-down resistance (90 k ? , 180 k ? )
chapter 4: input/out buffer and their use gate array S1L35000 series epson 25 design guide xidc (input cells) the xidc is a 5.0 v tolerant input buffer which can be used in a 3.0 v/3.3 v only asic application to satisfy mixed-voltage system requirements. table 4-6 table of input level shifters note: when ? value is 1 or 2, pull-down resistance value correspond to 1:90 k ? and 2:180 k ? respectively. 4.2.2.2 output buffer con?urations with a single 3.0/3.3v power supply when structuring the output buffer, use a combination of pre-drivers (such as xpdv1t, xpdv1at, xpdv2t, xpdv2at, etc.), which are structured of internal cells and output cells (such as xuom to xuo3). see table 4-7 below, regarding these combinations. cell name input level function pull-up/pull-down resistance xidc xidcd ? ttl ttl buffer buffer none pull-down resistance (90 k ? , 180 k ? )
chapter 4: input/out buffer and their use 26 epson gate array S1L35000 series design guide table 4-7 combinations of pre-drivers and output cells notes: * v ol = 0.3 v ( v dd = 3.3 v) refer to table 1-5 about the standard of i ol in v dd = 3.0v. ** v oh = v dd - 0.3 v ( v dd = 3.3 v ) refer to table 1-5 about the standard of i oh in v dd = 3.0v. *** in addition to the con?urations in table 4-7, the output buffers may be con?ured with pre-drivers which do not have test terminals. customers desiring to use such structures should direct inquiries to epson. ?xodn (open drain output cell) usage as is shown in table 4-8, con?ure open drain output functionality using the xodn output cell and pre-driver combinations with the n terminal connection only. do not connect the p terminal of the pre-driver output. (see figure 4-2). function i ol */i oh ** cell structure*** normal output for low noise 0.5ma/-0.5ma 2ma/-2ma 4ma/-4ma 6ma/-6ma xuom+xpdv1t xuo1+xpdv1t xuo2+xpdv1t xuo3+xpdv1t normal output for high speed 0.5ma/-0.5ma 2ma/-2ma 4ma/-4ma 6ma/-6ma xuom+xpdv1at xuo1+xpdv1at xuo2+xpdv1at xuo3+xpdv1at normal output with low slew rate control 0.5ma/-0.5ma 2ma/-2ma 4ma/-4ma 6ma/-6ma xuom+xpdv1bt xuo1+xpdv1bt xuo2+xpdv1bt xuo3+xpdv1bt normal output with slew rate control for fallling edge only 6ma/-6ma xuo3l+xpdv3t 3-state output for low noise 0.5ma/-0.5ma 2ma/-2ma 4ma/-4ma 6ma/-6ma xuom+xpdv2t xuo1+xpdv2t xuo2+xpdv2t xuo3+xpdv2t 3-state output for high speed 0.5ma/-0.5ma 2ma/-2ma 4ma/-4ma 6ma/-6ma xuom+xpdv2at xuo1+xpdv2at xuo2+xpdv2at xuo3+xpdv2at 3-state output with low slew rate control 0.5ma/-0.5ma 2ma/-2ma 4ma/-4ma 6ma/-6ma xuom+xpdv2bt xuo1+xpdv2bt xuo2+xpdv2bt xuo3+xpdv2bt 3-state output with slew rate control for falling edge only 6ma/-6ma xuo3l+xpdv4t
chapter 4: input/out buffer and their use gate array S1L35000 series epson 27 design guide table 4-8 combinations of pre-drivers and the xodn system cells notes * v ol = 0.3 v (v dd = 3.3 v) refer to table 1-5 about the standard of i ol in v dd = 3.0v. ** in addition to the structuring methods of table 4-8, the output buffers may be con?ured with pre-drivers which do not have test terminals. customers desiring to use such structures should direct inquiries to epson . 4.2.2.3 bi-directional buffer con?urations with a single 3.0/3.3 v power supply bi-directional buffers are con?ured from combinations of pre-drivers (with enable terminals) and bi-directional cells. (see figure 4-3. ) function i ol * cell structure** normal output for low noise 0.5ma 2ma 4ma 6ma xodnm+xpdv1t xodn1+xpdv1t xodn2+xpdv1t xodn3+xpdv1t normal output for high speed 0.5ma 2ma 4ma 6ma xodnm+xpdv1at xodn1+xpdv1at xodn2+xpdv1at xodn3+xpdv1at normal output with slew rate control 6ma xodn3l+xpdv3t
chapter 4: input/out buffer and their use 28 epson gate array S1L35000 series design guide table 4-9 combinations of pre-drivers and bi-directional cells notes: * v ol = 0.3 v (v dd = 3.3 v) refer to table 1-5 about the standard of i ol in v dd = 3.0v. ** v oh = v dd - 0.3 v (v dd = 3.3 v) refer to table 1-5 about the standard of i oh in v dd = 3.0v. *** in addition to the con?urations on table 4-9, bi-directional buffers may be con?ured with pre-drivers which do not have test terminals. most bi-directional buffers have two types of pull-up resistance options and two types of pull-down resistance options. customers desiring to use a pre-driver without test terminals should direct inquiries to epson. **** ttl input levels are not available when using a 3.0 v/3.3 v single power supply. input level function i ol */i oh ** cell structure cmos bi-directional for low noise output 0.5ma/-0.5ma 2ma/-2ma 4ma/-4ma 6ma/-6ma xucm+xpdv2t xuc1+xpdv2t xuc2+xpdv2t xuc3+xpdv2t cmos bi-directional for high speed output 0.5ma/-0.5ma 2ma/-2ma 4ma/-4ma 6ma/-6ma xucm+xpdv2at xuc1+xpdv2at xuc2+xpdv2at xuc3+xpdv2at cmos bi-directional with low slew rate control output 0.5ma/-0.5ma 2ma/-2ma 4ma/-4ma 6ma/-6ma xucm+xpdv2bt xuc1+xpdv2bt xuc2+xpdv2bt xuc3+xpdv2bt cmos bi-directional with slew rate control output for falling edge only 6ma/-6ma xuc3l+xpdv4t cmos schmitt bi-directional for low noise output 0.5ma/-0.5ma 2ma/-2ma 4ma/-4ma 6ma/-6ma xuhm+xpdv2t xuh1+xpdv2t xuh2+xpdv2t xuh3+xpdv2t cmos schmitt bi-directional for high speed output 0.5ma/-0.5ma 2ma/-2ma 4ma/-4ma 6ma/-6ma xuhm+xpdv2at xuh1+xpdv2at xuh2+xpdv2at xuh3+xpdv2at cmos schmitt bi-directional with low slew rate control output 0.5ma/-0.5ma 2ma/-2ma 4ma/-4ma 6ma/-6ma xuhm+xpdv2bt xuh1+xpdv2bt xuh2+xpdv2bt xuh3+xpdv2bt cmos schmitt bi-directional with slew rate control output for falling edge only 6ma/-6ma xuh3l+xpdv4t
chapter 4: input/out buffer and their use gate array S1L35000 series epson 29 design guide ? xbdc, xbdh system cells (bi-directional cells) xbdc and xbdh system cells are bi-directional cells which are constructed by combining xidc (5-volt tolerant input cells) and xodn (open drain output cells). table 4-10 gives combinations of pre-drivers and xbdc, xbdh system cells. table 4-10 combinations of pre-drivers and xbdc/xbdh system cells notes: * v ol = 0.3 v (v dd = 3.3 v) refer to table 1-5 about the standard of i ol in v dd = 3.0v. ** in addition to the con?urations in table 4-10, bi-directional buffers may be con?ured with pre-drivers which do not have test terminals. most bi-directional buffers have two types of pull-up resistance options and two types of pull-down resistance options. customers desiring to use structures without test terminals should direct inquiries to epson . input level function i ol * cell structure cmos bi-directional for low noise out- put 0.5ma 2ma 4ma 6ma xbdcm+xpdv2t xbdc1+xpdv2t xbdc2+xpdv2t xbdc3+xpdv2t cmos bi-directional for high speed output 0.5ma 2ma 4ma 6ma xbdcm+xpdv2at xbdc1+xpdv2at xbdc2+xpdv2at xbdc3+xpdv2at cmos bi-directional with low slew rate control output 0.5ma 2ma 4ma 6ma xbdcm+xpdv2bt xbdc1+xpdv2bt xbdc2+xpdv2bt xbdc3+xpdv2bt cmos bi-directional with slew rate control output 6ma xbdc3l+xpdv4t cmos schmitt bi-directional for low noise out- put 0.5ma 2ma 4ma 6ma xbdhm+xpdv2t xbdh1+xpdv2t xbdh2+xpdv2t xbdh3+xpdv2t cmos schmitt bi-directional for high speed output 0.5ma 2ma 4ma 6ma xbdhm+xpdv2at xbdh1+xpdv2at xbdh2+xpdv2at xbdh3+xpdv2at cmos schmitt bi-directional with low slew rate control output 0.5ma 2ma 4ma 6ma xbdhm+xpdv2bt xbdh1+xpdv2bt xbdh2+xpdv2bt xbdh3+xpdv2bt cmos schmitt bi-directional with slew rate control output 6ma xbdh3l+xpdv4t
chapter 4: input/out buffer and their use 30 epson gate array S1L35000 series design guide 4.3 oscillation circuit 4.3.1 oscillation circuit con?urations oscillation circuits should be con?ured, as shown in figure 4-4. both standard and gated oscillator circuit con?urations are supported as shown. figure 4-4 method of structuring the oscillator circuit 4.3.2 oscillator circuit considerations (1) pin layout the inputs and outputs of the oscillator circuits should be positioned on adjacent pins, and should be located between power supply pins (v dd , v ss ). do not locate high drive output pins near the input/output pins of the oscillator circuit. be especially careful to locate any outputs having the same phase or the opposite phase of the oscillating wave form as far as possible from the oscillator circuit input/output pins. whenever possible, locate the input/output pins of the oscillator circuit near the center of the edge of the package. (2) oscillator cell selection criteria the frequency at which oscillation is possible is approximately several 10 khz to mega-hertz (mhz). for details, please direct inquiries to epson. . lin lot lin lot gx d gx d e cg cd rf rd x'tal cg cd rf rd x'tal xa pa d pa d xa pa d pa d oscillation oscillation inside of ic inside of ic oscillation circuit with enable oscillation circuit without enable
chapter 4: input/out buffer and their use gate array S1L35000 series epson 31 design guide (3) selecting the values for the resistances and capacitors to be attached the characteristics of oscillation depends on the capacitive and resistive biasing elements. because of this, the capacitive and resistive values must be adjusted, depending on the crystal which will be used on the actual board. consequently, the optimal values should be chosen through spending adequate time evaluating available engineering samples. (4) assurance levels epson is unable to guarantee the function or characteristics of the oscillation. epson can warrantee only the oscillator cell. because of this, it is necessary for the customer to spend adequate time evaluating the engineering samples in terms of their oscillation characteristics. (5) discerning between xlot and xlot2 xlot and xlot2 are protected yet unbuffered line output cells. xlot2 is a low-impedance type xlot, used for situations where the oscillation frequency is high (>25 mhz). the selection of xlot vs. xlot2 is done in combination with the oscillator cell. direct inquiries for details to epson.
chapter 5: ram 32 epson gate array S1L35000 series design guide chapter 5 ram the S1L35000 series supports 1 port ram and 2 port ram. 5.1 features (1) 1-port ram ?asynchronous ?static operation ?1 read/write address port, 1 input data port, 1 output data port ?ram con?urations supported: word depth =16,32,64,96,128,192,256 bit width = 1 to 32 (incremental by 1 bit) ?3.0 v operation available (2) 2-port ram ?asynchronous ?static operation ?1 read address port, 1 write address port, 1 input data port, 1 output data port ?ram con?urations supported: word depth =16,32,64,96,128,192,256 bit width = 1 to 32 (incremental by 1 bit) ?3.0 v operation available 5.2 ram con?uration and simulation model selection ram delay parameters change depending on the word/bit structure. six simulation models (three 1-port ram models and three 2-port ram models) have been prepared using performance characteristics indicative to the ram word/bit con?uration. the 1-port ram and 2-port ram word/bit structure simulation models are shown in table 5-1 and 5.2 respectively . for ram with word/bit structures exceeding the limitations in the tables below, use combinations of multiple rams. table 5-1 simulation model selection chart (1-port ram word/bit structure) note: although each simulation model supports a variety of ram con?urations, the customer speci?d ram con?uration will be used during layout. number of words/bits 1 to 8 9 to 16 17 to 32 16, 32 xram4 xram5 xram6 64 xram5 xram5 xram6 96, 128 xram6 xram6 xram6 192, 256 xram7 xram7
chapter 5: ram gate array S1L35000 series epson 33 design guide table 5-2 simulation model selection chart (2-port ram word/bit structure) note: although each simulation model supports a variety of ram con?urations, the customer speci?d ram con?uration will be used during layout. 5.3 ram size the x-direction size, y-direction size, and number of bcs used in the ram are calculated using the formulas below. the formulas below include the interconnect region contained in the ram. use these formulas when investigating master selection when ram is included (see section 2.5). (1) 1-port ram a) for xram4, xram5, or xram6 size in the x direction: rx = 3 x word/2+j here, j=32; 1 bit 8 j=37; 9 bit 16 j=39; 17 bit 24 j=44; 25 bit 32 size in the y direction: ry = 2 x bit + k here, k=12; word = 16 k=13; word = 32 k=17; word 64 number of bcs:bc ram = rx x ry table 5-3 an example of the structure of 1-port ram note: the numbers within this chart indicate bc ram (rx x ry) which includes interconnect area. number of words/bits 1 to 8 9 to 16 17 to 32 16, 32 xram2p4 xram2p5 xram2p6 64 xram2p5 xram2p5 xram2p6 96, 128 xram2p6 xram2p6 xram2p6 192, 256 xram2p7 xram2p7 word/bit 4 8 16 32 16 1120 (56x20) 1568 (56x28) 2684 (61x44) 5168 (68x76) 32 1680 (80x21) 2320 (80x29) 3825 (85x45) 7084 (92x77) 64 3200 (128x25) 4224 (128x33) 6517 (133x49) 11340 (140x81) 96 4400 (176x25) 5808 (176x33) 8869 (229x49) 15228 (188x81) 128 5600 (224x25) 7392 (224x33) 11221 (325x49) 19116 (236x81) 192 8000 (320x25) 10560 (320x33) 15925 (325x49) 256 10400 (416x25) 13728 (416x33) 20629 (421x49)
chapter 5: ram 34 epson gate array S1L35000 series design guide (2) 2-port ram size in the x direction: rx = 3 x word /2+j here, j=32; 1 bit 8 j=37; 9 bit 16 j=39; 17 bit 24 j=44; 25 bit 32 size in the y direction: ry = 2 x bit + k here, k=14; word = 16 k=15; word = 32 k=21; word 64 number of bcs: bc ram = rx x ry table 5-4 an example of the structure of 2-port ram note: the numbers within this chart indicate bc ram (rx x ry), which includes interconnect area. word/bit 4 8 16 32 16 1232 (56x22) 1680 (56x30) 2806 (61x46) 5304 (68x78) 32 1840 (80x23) 2480 (80x31) 3995 (85x47) 7268 (92x79) 64 3712 (128x29) 4736 (128x37) 7049 (133x53) 11900 (140x85) 96 5104 (176x29) 6512 (176x37) 9593 (181x53) 15980 (188x85) 128 6496 (224x29) 8288 (224x37) 12137 (229x53) 20060 (236x85) 192 9280 (320x29) 11840 (320x37) 17225 (325x47) 256 12064 (416x29) 15392 (416x37) 22313 (410x47)
chapter 5: ram gate array S1L35000 series epson 35 design guide 5.4 investigating ram placement on master slice when investigating ram placement on a master slice, please insure that suf?ient area is available in both the x direction (column) and the y direction (row). when loading ram onto a chip, it is necessary to insure that the capacity of the master exceeds the required ram area in both the x and y directions. when multiple rams are used, ram blocks are placed adjacent to each other either horizontally or vertically; the decision regarding master slice selection is based simply on rx and ry. please see table 1-1 of chapter 1 regarding the number of columns (x-direction) and number of rows (y- direction). for example, if ?e 256word x 4 bit 1-port rams are required. as shown in figure 5-1, the total ram layout area would be: x direction: 416 bcs y direction: 125 bcs (25 x 5) because of this, s1l35043 is (x, y) = (499, 83) is impossible due to area constraints, however, s1l35063 is (x, y) = (480, 134) is possible. see section 2.5 pertaining to estimating the number of gates, bc awr , which can be used for random logic. figure 5-1 example of ram layout 256w x 4b ram 25 416 25 25 25 25 25 125 416 ram(1) ram(2) ram(3) ram(4) ram(5) x 5
chapter 5: ram 36 epson gate array S1L35000 series design guide 5.5 explanation of functions (1) 1-port ram table 5-5 1-port ram signals table 5-6 1-port ram truth table x: ? or ? ?data read the data is read by holding cs at ? and rw at ? and setting the address. ?data write the data can be written in either of the following two ways: (1) holding cs at ?? setting the address, and sending a negative pulse to rw. (2) holding rw at ?? setting the address, and sending a positive pulse to cs. when either method is used, the data is latched to the ram at the trailing edge of the pulse. ?the wait state when cs is ?? the 1 port ram enters a wait state and only maintains the data. the cur- rent consumed by the ram is merely the leakage current, and is almost zero. signal name i/o function notes cs in chip select signal, h: ram active fi = 1lu rw in read/write signal, h: read, l: write fi = 1lu a0, a1 ... a(m-1) in read/write address port, a0: lsb fi = 1lu d0, d1 ... d(n-1) in data input port, d0: lsb fi = 2lu y0, y1 ... y(n-1) out data output port, y0: lsb fo = 49lu corresponds to k:in2 cs rw a0, a1 ... a(m-1) y0, y1 ... y(n-1) mode 0 x x unknown wait 1 0 stable unknown write 1 1 stable read data read
chapter 5: ram gate array S1L35000 series epson 37 design guide (2) 2-port ram table 5-7 2-port ram signals table 5-8 2-port ram truth table x: ? or ? ?data read the data is read by holding cs at ? and rd at ? and setting the read address. ?data write the data can be written in either of the following two ways: (1)holding cs at ?? setting the write address, and sending a positive pulse to wr. (2)holding wr at ?? setting the write address, and sending a positive pulse to cs. ?data read/write when reading is done at the same time as writing, it is possible by performing the respec- tive methods simultaneously. however, these two operations cannot be performed simul- taneously on the same address. the read cycle access time applies to data for which the writing has already been completed. ?the wait state when cs is "l" ,the 1 port ram enters a wait state and only maintains the data. the cur- rent consumed by the ram is merely the leakage current, and is almost zero. signal name i/o function notes cs in chip select signal, h: ram active fi = 1lu rd in read signal, h: read enable fi = 1lu wr in write signal, h: write enable fi = 1lu ra0, . . . ra(m-1) in read address port, ra0: lsb fi = 1lu wa0, . . . wa(m-1) in write address port, wa0: lsb fi = 1lu d0, d1, . . . d(n-1) in data input port, d0: lsb fi = 2lu y0, y1, . . . y(n-1) out data output port, y0: lsb f0 = 49lu corresponds to k:in2 cs rd wr ra0, ... ra(n-1) wa0, ...wa(m-1) y0, ... y(n-1) mode 0xxxx unknown wait 1 0 0 x x unknown wait 1 0 1 x stable unknown write 1 1 0 stable x read data read 1 1 1 stable stable read data read & write
chapter 5: ram 38 epson gate array S1L35000 series design guide 5.6 delay parameters (1) 3.0 v speci?ations (v dd = 2.7 to 3.3v ; ta = -40 to 85 o c) table 5-9 1-port ram read cycle table 5-10 1-port ram write cycle parameter signal xram 4 xram 5 xram 6 xram 7 unit min. max. min. max. min. max. min. max. read cycle t rc 11.92 15.37 24.15 33.87 ns address access time t acc 11.92 15.37 24.15 33.87 cs access time t acs 11.47 14.77 23.25 32.71 r/w access time t arw 10.20 13.80 21.45 30.26 cs active time t rcs 11.92 15.37 24.15 33.87 output hold time after address change t oh 0.32 0.39 0.52 0.52 output hold time after cs disable t ohcs 0.32 0.39 0.52 0.52 output hold time after r/w disable t ohrw 0.33 0.45 0.52 0.52 parameter signal xram 4 xram 5 xram 6 xram 7 unit min. max. min. max. min. max. min. max. write cycle t wc 13.27 15.45 21.45 21.45 ns write pulse width t wp 9.07 10.72 15.60 15.60 cs active time t wcs 9.07 10.72 15.60 15.60 address setup time t as 1.87 2.17 2.70 2.70 address hold time t ah 2.32 2.62 3.15 3.15 data setup time t ds 2.92 3.30 4.20 4.20 data hold time t dh 4.05 6.60 9.30 9.30
chapter 5: ram gate array S1L35000 series epson 39 design guide table 5-11 2-port ram read cycle table 5-12 2-port ram write cycle parameter signal xram 2p4 xram 2p5 xram 2p6 xram 2p7 unit min. max. min. max. min. max. min. max. read cycle t rc 11.92 15.37 24.15 33.87 ns address access time t acc 11.92 15.37 24.15 33.87 cs access time t acs 11.47 14.77 23.25 32.71 rd access time t arw 10.20 13.80 21.45 30.26 cs active time t rcs 11.92 15.37 24.15 33.87 output hold time after address change t oh 0.32 0.39 0.52 0.52 output hold time after cs disable t ohcs 0.32 0.39 0.52 0.52 output hold time after rd disable t ohrw 0.33 0.45 0.52 0.52 parameter signal xram 2p4 xram 2p5 xram2p6 xram2p7 unit min. max. min. max. min. max. min. max. write cycle t wc 13.27 15.45 21.45 21.45 ns write pulse width t wp 9.07 10.72 15.60 15.60 cs active time t wcs 9.07 10.72 15.60 15.60 address setup time t as 1.87 2.17 2.70 2.70 address hold time t ah 2.32 2.62 3.15 3.15 data setup time t ds 2.92 3.30 4.20 4.20 data hold time t dh 4.05 6.60 9.30 9.30
chapter 5: ram 40 epson gate array S1L35000 series design guide (2) 3.3 v speci?ations (v dd = 3.0 to 3.6v ; ta = -40 to 85?) table 5-13 1-port ram write cycle table 5-14 1-port ram write cycle parameter signal xram 4 xram 5 xram 6 xram 7 unit min. max. min. max. min. max. min. max. read cycle t rc 10.42 13.50 21.22 30.35 ns address access time t acc 10.42 13.50 21.22 30.35 cs access time t acs 10.05 12.97 20.40 29.19 r/w access time t arw 8.92 12.15 18.82 27.61 cs active time t rcs 10.42 13.50 21.22 30.35 output hold time after address change t oh 0.29 0.36 0.50 0.50 output hold time after cs disable t ohcs 0.29 0.36 0.50 0.50 output hold time after r/w disable t ohrw 0.30 0,42 0.53 0.53 parameter signal xram 4 xram 5 xram 6 xram 7 unit min. max. min. max. min. max. min. max. write cycle t wc 11.62 13.57 18.82 18.82 ns write pulse width t wp 7.95 9.37 13.65 13.65 cs active time t wcs 7.95 9.37 13.65 13.65 address setup time t as 1.65 1.95 2.40 2.40 address hold time t ah 2.02 2.25 2.77 2.77 data setup time t ds 2.55 2.92 3.67 3.67 data hold time t dh 3.52 5.77 8.17 8.17
chapter 5: ram gate array S1L35000 series epson 41 design guide table 5-15 2-port ram read cycle table 5-16 2-port ram write cycle parameter signal xram 2p4 xram 2p5 xram 2p6 xram 2p7 unit min. max. min. max. min. max. min. max. read cycle t rc 10.42 13.50 21.22 30.35 ns address access time t acc 10.42 13.50 21.22 30.35 cs access time t acs 10.05 12.97 20.40 29.19 rd access time t arw 8.92 12.15 18.82 27.61 cs active time t rcs 10.42 13.50 21.22 30.35 output hold time after address change t oh 0.29 0.36 0.50 0.50 output hold time after cs disable t ohcs 0.29 0.36 0.50 0.50 output hold time after rd disable t ohrw 0.30 0.42 0.53 0.53 parameter signal xram 2p4 xram 2p5 xram2p6 xram2p7 unit min. max. min. max. min. max. min. max. write cycle t wc 11.62 13.57 18.82 18.82 ns write pulse width t wp 7.95 9.37 13.65 13.65 cs active time t wcs 7.95 9.37 13.65 13.65 address setup time t as 1.65 1.95 2.40 2.40 address hold time t ah 2.02 2.25 2.77 2.77 data setup time t ds 2.55 2.92 3.67 3.67 data hold time t dh 3.52 5.77 8.17 8.17
chapter 5: ram 42 epson gate array S1L35000 series design guide (3) 5.0 v ?5% speci?ations (v dd = 4.75 to 5.25v; ta = 0 to 70?) table 5-17 1-port ram read cycle table 5-18 1-port ram write cycle table 5-19 2-port ram read cycle parameter signal xram 4 xram 5 xram 6 xram 7 unit min. max. min. max. min. max. min. max. read cycle t rc 5.92 7.57 11.70 16.74 ns address access time t acc 5.92 7.57 11.70 16.74 cs access time t acs 5.70 7.27 11.17 15.79 r/w access time t arw 5.32 6.75 10.12 13.96 cs active time t rcs 5.92 7.57 11.70 16.74 output hold time after address change t oh 0.26 0.32 0.44 0.44 output hold time after cs disable t ohcs 0.27 0.33 0.45 0.45 output hold time after r/w disable t ohrw 0.27 0.33 0.45 0.45 parameter signal xram 4 xram 5 xram 6 xram 7 unit min. max. min. max. min. max. min. max. write cycle t wc 8.02 9.22 11.92 11.92 ns write pulse width t wp 5.55 6.52 8.40 8.40 cs active time t wcs 5.55 6.52 8.40 8.40 address setup time t as 1.12 1.20 1.50 1.50 address hold time t ah 1.35 1.50 2.02 2.02 data setup time t ds 1.65 1.87 2.32 2.32 data hold time t dh 2.85 3.60 5.10 5.10 parameter signal xram 2p4 xram 2p5 xram 2p6 xram 2p7 unit min. max. min. max. min. max. min. max. read cycle t rc 5.92 7.57 11.70 16.74 ns address access time t acc 5.92 7.57 11.70 16.74 cs access time t acs 5.70 7.27 11.17 15.79 rd access time t arw 5.32 6.75 10.12 13.96 cs active time t rcs 5.92 7.57 11.70 16.74 output hold time after address change t oh 0.26 0.32 0.44 0.44 output hold time after cs disable t ohcs 0.27 0.33 0.45 0.45 output hold time after rd disable t ohrw 0.27 0.33 0.45 0.45
chapter 5: ram gate array S1L35000 series epson 43 design guide table 5-20 2-port ram write cycle parameter signal xram 2p4 xram 2p5 xram2p6 xram2p7 unit min. max. min. max. min. max. min. max. write cycle t wc 8.02 9.22 11.92 11.92 ns write pulse width t wp 5.55 6.52 8.40 8.40 cs active time t wcs 5.55 6.52 8.40 8.40 address setup time t as 1.12 1.20 1.50 1.50 address hold time t ah 1.35 1.50 2.02 2.02 data setup time t ds 1.65 1.87 2.32 2.32 data hold time t dh 2.85 3.60 5.10 5.10
chapter 5: ram 44 epson gate array S1L35000 series design guide (4) 5.0v ?10% speci?ations (v dd = 4.5 to 5.5v ; ta = -40 to 85?) table 5-21 1-port ram read cycle table 5-22 1-port ram write cycle parameter signal xram 4 xram 5 xram 6 xram 7 unit min. max. min. max. min. max. min. max. read cycle t rc 6.30 8.10 12.52 17.85 ns address access time t acc 6.30 8.10 12.52 17.85 cs access time t acs 6.08 7.80 12.00 16.90 r/w access time t arw 5.70 7.20 10.87 15.04 cs active time t rcs 6.30 8.10 12.52 17.85 output hold time after address change t oh 0.23 0.28 0.39 0.39 output hold time after cs disable t ohcs 0.24 0.28 0.39 0.39 output hold time after r/w disable t ohrw 0.24 0.29 0.39 0.39 parameter signal xram 4 xram 5 xram 6 xram 7 unit min. max. min. max. min. max. min. max. write cycle t wc 8.62 9.90 12.80 12.80 ns write pulse width t wp 6.00 6.97 9.00 9.00 cs active time t wcs 6.00 6.97 9.00 9.00 address setup time t as 1.20 1.35 1.65 1.65 address hold time t ah 1.42 1.57 2.17 2.17 data setup time t ds 1.80 2.02 2.55 2.55 data hold time t dh 3.07 3.90 5.47 5.47
chapter 5: ram gate array S1L35000 series epson 45 design guide table 5-23 2-port ram read cycle table 5-24 2-port ram write cycle parameter signal xram 2p4 xram 2p5 xram 2p6 xram 2p7 unit min. max. min. max. min. max. min. max. read cycle t rc 6.30 8.10 12.52 17.85 ns address access time t acc 6.30 8.10 12.52 17.85 cs access time t acs 6.08 7.80 12.00 16.90 rd access time t arw 5.70 7.20 10.87 15.04 cs active time t rcs 6.30 8.10 12.52 17.85 output hold time after address change t oh 0.23 0.28 0.39 0.39 output hold time after cs disable t ohcs 0.24 0.28 0.39 0.39 output hold time after rd disable t ohrw 0.24 0.29 0.39 0.39 parameter signal xram 2p4 xram 2p5 xram2p6 xram2p7 unit min. max. min. max. min. max. min. max. write cycle t wc 8.62 9.90 12.80 12.80 ns write pulse width t wp 6.00 6.97 9.00 9.00 cs active time t wcs 6.00 6.97 9.00 9.00 address setup time t as 1.20 1.35 1.65 1.65 address hold time t ah 1.42 1.57 2.17 2.17 data setup time t ds 1.80 2.02 2.55 2.55 data hold time t dh 3.07 3.90 5.47 5.47
chapter 5: ram 46 epson gate array S1L35000 series design guide 5.7 timing charts (1) 1-port ram figure 5-2 read cycle figure 5-3 write cycle (r/w control) t oh xx x x t ohcs t acs t acc t acc t ohrw t arw a1 a2 a3 address cs rw data out t rcs t rc a1 a1 a2 a3 a3 t wc t as t wp t dh t ah address cs rw data in valid t ds
chapter 5: ram gate array S1L35000 series epson 47 design guide figure 5-4 write cycle (cs control) (2) 2-port ram figure 5-5 read cycle t wc t as t wcs t dh t ah address cs rw data in valid t ds t oh xx x x t ohcs t acs t acc t acc t ohrw t arw a1 a2 a3 address cs rd data out t rcs t rc a1 a1 a2 a3 a3
chapter 5: ram 48 epson gate array S1L35000 series design guide figure 5-6 write cycle (write control) figure 5-7 write cycle (cs control) t wc t as t wp t dh t ah address cs wr data in valid t ds t wc t as t wcs t dh t ah address cs wr data in valid t ds
chapter 5: ram gate array S1L35000 series epson 49 design guide 5.8 ram test method when it comes to internal ram, specialized tests are performed corresponding to the ram, separate from the ramdom logic. please structure test circuits which facilitate direct access to the internal ram from external pins for this purpose. see section 6.3 of chapter 6 regarding the method of structuring the ram test circuits. also, although epson will generate an independent test pattern for the ram, the customer should provide test patterns for the remaining random logic, in addition to a ram test pattern template, as shown in section 6.3.1. 5.9 estimating ram current consumption the method for estimating the current consumption at v dd (typ.) = 5.0 v is given below. moreover, for v dd (typ.) = 3.0 v or 3.3 v, the value is approximately 0.6 (60%) of the value which is calculated using the method shown below. at standby (cs = 0) : 0 [?/bit] during operation (cs = 1) : [(-1.5x 2 + 832x) * 10 -4 + 2.0y + 6.075] * f x : words y : bits f : mh z (average access cycles) 5.10 ram symbols and how they are used when the 1 port ram uses a 32 word x 8 bit structure, the use of symbols is as given in figure 5-8. this structure requires 5 address pins and 8 data input pins. as is shown in figure 5-8, any unused address pins or data input pins should be tied to ? or ? beginning with the most signi?ant bits. furthermore, if multiple rams are used, the circuit shoud be con?ured by using the same numbers of symbols as rams.
chapter 5: ram 50 epson gate array S1L35000 series design guide figure 5-8 example of the use of ram symbols (xram4: 32 words x 8 bits) d0 d1 d2 d3 d4 d5 d6 d7 d8 d31 . . . . . . . . . . a 0 a 1 a 2 a 3 a 4 a 5 a 6 r w c s y0 y1 y2 y3 y4 y5 y6 y7 y8 y31 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . application circuit application xram4 circuit
chapter 6: circuit design taking testability into account gate array S1L35000 series epson 51 design guide chapter 6 circuit design taking testability into account before a gate array is shipped the product is tested using an lsi tester. it is necessary to design the circuit keeping testability in mind to facilitate this testing. when designing the circuit, the following points should be carefully considered. 6.1 considerations regarding circuit initialization when testing ics using an lsi tester, or when verifying circuit functionality using a software simulator, the initial state of all sequential element is x (unknown). consequently, very large test patterns may be necessary, depending on the circuit structure, to initialize the sequential elements or it may not be possible to initialize the circuits at all. because of this, the circuits should be structured to facilitate easy initialization when they are designed (for example, by using sequential elements which have reset, set or preset functions). 6.2 considerations regarding compressing the test patterns as the gate densities of circuits increase, there is a tendency for test patterns to become larger as well. however, one must understand that there are constraints, such as shown below, to the lsi device tests. number of events per test pattern: 64k events or less number of test patterns: 20 test patterns or less total number of test pattern events: 256k events or less these event and test pattern constraints include the test patterns for test patterns for leakage testing, test patterns for test circuits, and the test patterns for ram/rom and megacell testing (prepared by epson). direct inquiries regarding the number of test patterns and number of events per test pattern for the ram/rom and megacell testing to epson. when designing, please structure circuits in such a way as to increase the testability of the circuit (and to allow the compression of the test patterns), using methods such as including test pins which allow the input of clocks between the counter stages and adding test pins by which to monitor internal signals.
chapter 6: circuit design taking testability into account 52 epson gate array S1L35000 series design guide 6.3 ram test circuit when a ram is used it is necessary to test all bits before shipping the product. ram terminals must be accessible via primary i/o pins. ram test circuitry can be implemented, which multiplexes existing pin functionality with direct ram access functionality so as to avoid increasing the designs pin count. also, when multiple rams are used, we recommend that each rams pins be accessible via unique i/o pins. however, when the number of external i/o pins is inadequate, each rams pins may share common external i/o pins. please insure that while in ram test mode, all ram cs pins can be held ? simultaneously to facilitate quiescent current meas urement. figure 6-1 is an example of a test circuit for two word x 2 bit rams. when the test pin ?est is ?? then normal functioning is performed. however, when the test pin ?est is ?? then the external pins ics, irw, id0, id1, and ia0 can write data directly to the ram, and at the same time the ram outputs can be read from the external pins ay0 and ay1. although it is possible to share the ram pins with bi-directional pins or 3-state output pins, it is necessary to tie the bi-directional pins to either an input or an output state during ram test. however, please do not share a bi-directional cell with a pull-up resistor with the ram output, and do not share a input cell with a pull-up with the ram cs pin, because doing so would make it impossible to measure the quiescent current. when multiple rams are used, all ram cs pins can be held ? simultaneously to facilitate quiecent current measurement.
chapter 6: circuit design taking testability into account gate array S1L35000 series epson 53 design guide figure 6-1 example of a ram test circuit 6.3.1 ram test pattterns after incorporating ram test circuitry, it is necessary to make test patterns for both the normal operating state and the test state of the chip. checks are performed in the normal state to verify the connection with the user circuits, and are performed to insure that the test circuit is correct in the test state. also, we request a test pattern to serve as a template when epson generates the ram test pattern. see figure 6-2 and 6.3 for an outline of how to generate this test pattern. xram4 cs d0 d1 d2 d3 d4 d5 d6 d7 d8 d9 d10 d11 d12 d13 d14 d15 d16 d17 d18 d19 d20 d21 d22 d23 d24 d25 d26 d27 d28 d29 d30 d31 y0 y1 y2 y3 y4 y5 y6 y7 y8 y9 y10 y11 y12 y13 y14 y15 y16 y17 y18 y19 y20 y21 y22 y23 y24 y25 y26 y27 y28 y29 y30 y31 ay0 ay1 by0 by1 ia0 id0 irw1 ics1 irw2 ics1 test id1 xuo3 i_5 ap n xpdv1t i_6 xao24a i_10 xuo3 i_4 ap n xpdv1t i_7 xuo3 i_3 ap n xpdv1t i_6 xao24a i_9 xut3 i_1 ap n xpdv2t i_2 xao24a i_11 e xao24a i_35 xibc i_29 xibc i_28 xut4 i_32 a p n xpdv2t i_33 e xao24a i_34 xibc i_26 xibc i_25 xibc i_24 xibc i_23 xibc i_22 xao24a i_12 xao24a i_21 xao24a i_20 xao24a i_19 xao24a i_18 xao24a i_17 xao24a i_16 xao24a i_15 xao24a i_14 xao24a i_13 xram4 customer's circuit a0 a1 a2 a3 a4 a5 a6 a0 a1 a2 a3 a4 a5 a6 cs i_31 i_30 d0 d1 d2 d3 d4 d5 d6 d7 d8 d9 d10 d11 d12 d13 d14 d15 d16 d17 d18 d19 d20 d21 d22 d23 d24 d25 d26 d27 d28 d29 d30 d31 y0 y1 y2 y3 y4 y5 y6 y7 y8 y9 y10 y11 y12 y13 y14 y15 y16 y17 y18 y19 y20 y21 y22 y23 y24 y25 y26 y27 y28 y29 y30 y31 td te ts td ts td ts td ts td te ts rw rw a7 a7
chapter 6: circuit design taking testability into account 54 epson gate array S1L35000 series design guide x (1) setup a [2 : 0] r w y [3 : 0] cs d [3 : 0] x (read data) strobe expect (2) write (3) read x (2) write (2) write ram signals aaaddddrc 0120123ws yyyy 0123 0000000000 0000 .. .. 0000000001 1111 .. .. 1234567890 1234 .. .. iiiiiiiiit oooo .. .. nnnnnnnnne uuuu .. .. .. .. ppppppppps tttt .. .. abcdefghit abcd .. e .. n 2 .. .. .. iiiiiiiiii oooo 0 .. 0 .. 0 .. 0000000000 .. 1000000 .. .. xxxx 0 0001010101 .. .. xxxx 1 0001010n11 .. .. hlhl 2 0001010111 .. .. xxxx 3 1011111101 .. .. xxxx 4 1011111n11 .. .. hhhh 5 1011111111 .. .. xxxx 6 1110101101 .. .. xxxx 7 1110101n11 .. .. lhlh 8 1110101111 * * * $clo inph 500000 this pattern serves as a template for 1-port ram tests it is useful to place comments here. please provide all i/o pins used in reference the timing chart below to set timing. when a sequence is necessary to set the test mode, input the pattern here. [1] access the lowest address, a middle address [2] structure a single access from 3 events (test [3] use an rz waveform to describe the rw signal [4] change the data to be written for each address [5] verify that the results are the same as expected the tester may perform repetitive write operations with the timing shown in the timing performing simulation. and the highest address. cycles). in the first event, set the data and the address. in the next event, perform a write. in so that the write operation can be completed in a single event. tested. from the results of the simulations. the third event, perform a read. chart on the right. the timing of the rw signal should take this into account. timing chart figure 6-3 generating the ram test pattern
chapter 6: circuit design taking testability into account gate array S1L35000 series epson 55 design guide $rate 200000 $strobe 185000 $resolution 0.001ns $node inpa i 0 inpb i 0 inpc i 0 inpd i 0 inpe i 0 inpf i 0 inpg i 0 inph i 0 inpi p 20000 520000 inpj i 0 testen i 0 . outa 0 outb 0 outc 0 outd 0 . . $endnode $pattern 0 00010100001.xxxx.. 1 00010100p11.xxxx.. 2 00010101011.hlhl.. 3 10111110001.xxxx.. 4 10111110p11.xxxx.. 5 10111111011.hhhh.. 6 11101010001.xxxx.. 7 11101010p11.xxxx.. 8 11101011011.lhlh.. example of test pattern for 2-port ram (apf format)
chapter 6: circuit design taking testability into account 56 epson gate array S1L35000 series design guide x (1) setup a [2 : 0] wr y [3 : 0] cs d [3 : 0] x (read data) strobe expect (2) write (3) read x r d (2) write (2) write ram signals aaaddddrwc 0120123drs yyyy 0123 * * * $clo inpi 500000 ... xxxx 0 00010100001 ... xxxx 1 00010100p11 ... hlhl 2 00010101011 ... xxxx 3 10111110001 ... xxxx 4 10111110p11 ... hhhh 5 10111111011 ... xxxx 6 11101010001 ... xxxx 7 11101010p11 ... lhlh 8 11101011011 00000000200 . ... iiiiiiiiiii oooo 00000000000 . 00000000000 . 00000000000 . 00000000000 . 1000000 00000000000 0000 ... 00000000011 1111 ... 12345678901 2345 ... iiiiiiiiiit oooo ... nnnnnnnnnne uuuu ... ... pppppppppps tttt ... abcdefghijt abcd . e . n this pattern serves as a template for 2-port ram tests it is useful to place comments here. please provide all i/o pins used in reference the timing chart below to set timing. when a sequence is necessary to set the test mode , input the pattern here. [1] access the lowest address, a middle address [2] structure a single access from 3 events (test [3] use an wrwaveform to describe the wrsignal [4] change the data to be written for each address [5] verify that the results are the same as expected the tester may perform repetitive write operations with the timing shown in the performing simulation. and the highest address. cycles). in the first event, set the data and the address. in the next event, perform a write. in so that the write operation can be completed in a single event. tested. from the results of the simulations. the third event, perform a read. timing chart on the right. the timing of the wr signal should take this into account. timing chart figure 6-3 generating the ram test pattern
chapter 6: circuit design taking testability into account gate array S1L35000 series epson 57 design guide $rate 200000 $strobe 185000 $resolution 0.001ns $node inpa i 0 inpb i 0 inpc i 0 inpd i 0 inpe i 0 inpf i 0 inpg i 0 inph i 0 inpi p 20000 520000 inpj i 0 testen i 0 . outa 0 outb 0 outc 0 outd 0 . . $endnode $pattern 0 00010100001.xxxx.. 1 00010100p11.xxxx.. 2 00010101011.hlhl.. 3 10111110001.xxxx.. 4 10111110p11.xxxx.. 5 10111111011.hhhh.. 6 11101010001.xxxx.. 7 11101010p11.xxxx.. 8 11101011011.lhlh.. example of test pattern for 2-port ram (apf format)
chapter 6: circuit design taking testability into account 58 epson gate array S1L35000 series design guide 6.4 function cell test circuits when function cells are used, then testing the operation of all circuits (including the user circuits) requires a vast number of test patterns and a great amount of time. it is because of this that it is necessary to design test circuits able to verify the operation of each independent functional cell and user circuit, as was done with the ram blocks. when designing the test circuits, please keep the following cautions and considerations in mind. for more details, contact epson. 6.4.1 test circuit structures (1) provide test circuitry which facilitates direct access to all pins of each functional cell via i/o pins. add a test circuit (connected to a terminal) which isolates each functional cell from the surrounding circuits. (2) even when functional cell input pins are ?ed to logic 0 or logic 1, design test circuitry which insures access to all functional cell pins. (3) even when functional cell output pins are not used, design test circuitry which insures access to all functional cell pins. (4) each functional cell pin must be connected to a unique i/o pin. (5) do not use sequential elements in the test circuitry for functional cells. (6) do not invert the input signal from the test input terminal and input it into the functional cell. similarly, do not invert the functional cell output signal and output it to the test output terminal. (7) there is no need to design a test circuit when the functional cell input pins and output pins are directly connected to the i/o pins. (8) do not use an input cell with pull-up or a bi-directional cell with pull-up as the test mode switch pin (although a bi-directional cell with pull-down may be used). 6.4.2 test patterns the test patterns can be categorized into the following two types: 1) test patterns to test only the users circuit. 2) test patterns to test all circuits. 3) test patterns to test the functional cells only. test patterns that the customers generateare of type 1 and 2. customers are not required to generate test patterns of type 3. epson maintains test patterns to be used for type 3. please be advised that epson will not disclose information pertaining to the functional cell test patterns.
chapter 6: circuit design taking testability into account gate array S1L35000 series epson 59 design guide 6.4.3 test circuit data please provide the following information regarding functional test circuitry. this information is required for functional cell testing during simulation and ic device testing. (1) please clearly de?e the i/o pin to functional cell pin connectivity while in test mode. (2) when the test circuits are structured in such a way that a single test terminal is able to test multiple functional cells, please clearly de?e the names of the functional cells which can be selected and the type of the test modes, and their relationships. (3) please clearly de?e pass numbers on the names of the functional cells on the drawings, and clearly de?e the test terminals and their association with functional cells, especially when identical functional cells are used more than once. (4) please clearly de?e the method of switching into test mode.
chapter 6: circuit design taking testability into account 60 epson gate array S1L35000 series design guide 6.5 test circuit which simpli?s ac and dc testing t est circuit str ucture the S1L35000 series requires the construction of test circuits so that dc testing and ac testing can be done ef?iently. if the customer experiences dif?ulties while implementing test circuitry, then the customer should contact epson. figure 6-4 shows speci? examples of test circuits. this ?ure should be referenced when designing test circuits. recommended test circuit control and monitor pin con?urations are shown below. (1) test circuit control and monitor pins please add or select the following 4 types of test pins. ?dedicated input pin for testing: 1 pin ?test mode select input pin: 3 pins (can be functionally shared with input pins of application) ?monitor output pin for ac testing: 1 pin (can be functionally shared with output pin of application) table 6-1 table of test terminal constraints (2) measurements are performed to insure that all input and output pins adhere to dccharacteristic speci?ations. when test circuitry is not implemented, it is necessary for the customer to generate test patterns by which the dc characteristics can be measured. the amount of work in generating the test patterns may increase dramatically when there are no test circuits. the task of generating test patterns and measuring the dc chracteristics is simpli?dby using test circuits. test pin type number of pins name of pins (see fig. 6.4) constraints, notes, etc. test enable pin 1 pin tsten dedicated input pin use xitst1. h: test mode l: normal mode test mode pins 3 terminals inp0 inp1 inp2 may be shared with existing input pin. do not share with an input pin associated with a critical path. monitor output pin for ac testing 1pin out3 may be shared with existing output pin. do not share with a bidirectional, 3-state terminal or with an n-channel open- drain cell. all output and bi-direc- tional pins -- -- uses pre-drivers with test mode select (when comparing usual pre-drives, three or four gates for a pin are added.)
chapter 6: circuit design taking testability into account gate array S1L35000 series epson 61 design guide (3)ac testing ac testing is a pin-to-pin (i.e. input pin to output pin) delay measurement. if device testing is not performed at actual operating frequency, device performance is assured through delay measurements along speci? paths. also, the ac test monitor output pin is used to evaluate the variance between lots in the manufacturing process by measuring a de?ed ac path (cell name: xacp1). (when test circuits are used, be sure to insert cell xacp1 when designing the ac path test circuit.) (4) adding the test mode control circuit the following items (a through j) pertain to test circuit implementation. please refer to the test circuit examples of figure 6-4. a. select 4 test input pins and 1 output pin ?dedicated input pin for testing: 1 pin (test enable signal:two pins if it is possible.) ?test mode select input pin: 3 pins (can be functionally shared with input pins of application) ?monitor output pin for ac testing: 1 pin (can be functionally shared with output pin of application) b. the dedicated input pin for test enable/disable (tsten) must use cell xitst1. c. the dedicated or shared input pins for test mode selection (inp0, inp1 and inp2) can use any input buffer cell type. avoid sharing these test inputs with critical path input pins of the application. d. the dedicated or shared output pins for ac monitoring (out3) can use any uni-directional output buffer type (except 3-state type). avoid sharing these test outputs with critical path output pins of the application. e. all pre-drivers for output and bi-directional pin con?urations must have test mode functionality. f. please utilize the test mode control circuit (tcir). g. the primary test enable/disable signal (output pin ?n of cell xitst1) should be connected to the ?st input pin of functional block tcir. when this signal is enabled (set to logic ??, the test mode control circuitry (block tcir) becomes functional and facilitates ac and quiescent current testing.
chapter 6: circuit design taking testability into account 62 epson gate array S1L35000 series design guide h. three dedicated shared input signals (output pins of uni-directional input buffer cells) should be connected to the ?p0? ?p1 and ?p2 input pins of functional block tcir. a ?st dedicated/shared input signal (inp0 in figure 6-4) should be connected to input pin ?p0 of functional block tcir. this signal will control the mode of all bi-directional i/o cells which utilize pre-drivers with test functionality. when ?p0 is state ? and ?p2 is state ? , all bi-directional i/o will be placed in input mode, and all 3-state outputs will be in high- impedance state. when ?p0 is state ?? all bi-directional and 3-state i/o will be in output mode. a second dedicated/shared input signal (inp1 in figure 6-4) should be connected to input pin ?p1 of functional block tcir. this signal controls output data while in test mode. the data which appears at pin ?p1 will be passed to all output and bi-directional i/o cells when ?p2 is state ? . a third dedicated/shared input signal (inp2 in figure 6-4) should be connected to input signal pin ?p2 of functional block tcir. this signal controls all output and bi-directional signals excluding the ac monitor output pin during ac testing. when input signal ?p2 is state ? and all outputs remain in stable state ? so as to minimize switching noise during ac testing. i. the following describes the recommended connections for the output pins of the test circuit functional block tcir. the tcir output pin ?co is used for ac characterization testing. this output of tcir must be connected to one and only one ?d input pin of a user selected pre-driver (out3), which is connected to a uni-directional output driver (not 3-state). the tcir output pin ?s is the test mode control signal. this output is used to put all pre- drivers connected to output and bi-directional i/os into test mode. when ?s is state ?? all pre-drivers are in test mode. the tcir output pin ?e is used for test mode bi-directional enable (or control). this output is connected to all 3-state and bi-directional pre-drivers ?e input pin. when ?e is state ?? all 3-state (out2) and bi-directional drivers (bid1) are placed in output mode. j. fan-out violations which may occur on tcir output pins ?s? ?d and ?e can be ignored.
chapter 6: circuit design taking testability into account gate array S1L35000 series epson 63 design guide (5) setting the test mode (please refer to figure 6-4) ?output characteristics (v oh /v ol ) measurement mode tsten . . . high inp0 . . . high inp1 . . . high for v oh test and low for v ol test inp2 . . . this controls the bi-directional and 3-state pin mode high . . . hi-z (input) mode* low . . . output mode * can be used as 3-state and bi-directional off-state leakage current measurement mode. ?edicated ac path measurement mode tsten . . . high inp0 . . . low inp1 . . . change from high to low, then change from low to high out3 . . . is used to monitor delay from inp1 inp2 . . . high gener ating the t est p atter n it is necessary for the customer to design test patterns at the same time that the customer designs the test circuits so that the dc testing and the ac testing can be performed in an ef?ient manner. figure 6-5 shows a speci? example of the test pattern related to the test circuits in figure 6-4. the following should be kept in mind when generating the test patterns: a. please generate a test pattern to exercise test circuitry separate from standard application functional test patterns. b. test circuit test patterns must specify all input, output and bi-directional i/o signals. c. please insure that the dedicated test enable pin (i.e. testen in figure 6-4) is present and set to state ? in the standard application functional test patterns. d. when the input level (tsten) of test terminal is set to ? all pull-up resistance are non- active (off).
chapter 6: circuit design taking testability into account 64 epson gate array S1L35000 series design guide chapter 6: circuit design taking testability into account gate array S1L35000 series epson 65 design guide figure 6-5 example of the generation of a test pattern when there is a test option 0000000000 0000000001 1234567890 tiiiibbooo snnnniiuuu tppp ddttt e012 11123 n x i 1000000 iiiiii0000 000000 0 0.....xxxx 1 10.0..xxxx 2 1001..hhhl 3 1011..hhhh 4 1001..hhhl 5 1101.0zhzl 6 1111.1zhzh 7 1100..llll 8 1110..hhhh ? example of test pattern for ac & dc test (press format) ;pull-up/down off ;ac path (l), other output all high ;ac path (h), other output all high ;ac path (l), other output all high ;off state except normal output (low input) ;off state except normal output (high input) ;output all low ;output all high note) "." is 1 or 0 input.
chapter 6: circuit design taking testability into account 66 epson gate array S1L35000 series design guide figure 6-6 example of the generation of a test pattern when there is a test option $design testckt $rate 200000 $strobe 185000 $resolution 0.001ns $iocont aa08.e e0 bid1 $endiocont $node testen i 0 inp0 i 0 inp1 i 0 inp2 i 0 in i 0 bid1 bu 0 out1 0 out2 0 out3 0 $endnode $pattern example of test pattern for ac & dc test (apf format) pull-up/down off ac path (l), other output all high ac path (h), other output all high ac path (l), other output all high off state except normal output (low input) off state except normal output (high input) output all low output all high tiiiibooo snnnniuuu tppp dttt e012 1123 n iiiiibooo u # # # # # # # # # 0....xxxx 10.0.xxxx 1001.hhhl 1011.hhhh 1001.hhhl 1101.0hzl 1111.1hzh 1100.llll 1110.hhhh 0 1 2 3 4 5 6 7 8 $ endpattern # # eof note) "."is 1 or 0 input. # # # # # # # #
chapter 7: propagation delay and timing gate array S1L35000 series epson 67 design guide chapter 7 propagation delay and timing propagation delay time is determined by the intrinsic cell delay and by the per-load delay, which is a function of the wire interconnect and fan-in capacitances. delay times vary depending upon power supply voltage, ambient temperature, and process conditions. they also vary depending on factors involved in the structure of the circuit, input waveform, input logic level, and the mirror effect. post simulation uses more acculate environment. 7.1 simple delay models simple propagation delay time t pd can be calculated using the following formula: t pd = t 0 + k x (?oad a + load b) where, t 0 : intrinsic cell delay [ps] k: load delay coef?ient [ps/lu] load a: the input load capacitance due to fan-in [lu] load b: the interconnect load capacitance [lu] note: the values for t 0 and k differ depending upon the operating voltage, the ambient temperature, and the process conditions. use the values provided in the ?ate array S1L35000 series msi cell library. the unit ?u stands for loading unit, which is equivalent to one ?in1 input fan-in. typ. values for t 0 and k (v dd = nominal value, ta = 25 o c, and process = nominal value) are found in the ?ate array S1L35000 series msi cell library. select typ. values for t 0 and k according to the target power supply voltage.the min. value for t 0 and k (where v dd is the max. value, ta = min. value and process = fast) and the max. value for t 0 and k (where v dd = min. value, ta = max. value, and process = slow) are calculated by multiplying the typ. value, described above, by the delay coef?ient m. (these min. and max. values are required to verify asic operation over commercial and industrial variances in supply voltage, ambient temperature and process.) the delay coef?ient m can be calculated using the following formula: m = m v x m t x m p where, m v : delay multiplier due to voltage variation m t : delay multiplier due to temperature variation m p : delay multiplier due to process variation although values for m v and m t can be obtained by reading them off of the characteristic graphs in the ?ate array S1L35000 series msi cell library, please use the duration delay coef?ient vaues m, given in table 7-1. also, please direct inquiries to the epson regarding asic operation outside of the limits shown in table 7-1.
chapter 7: propagation delay and timing 68 epson gate array S1L35000 series design guide note 1:the typ. value for v dd = 3.0 v is not listed in the ?ate array S1L35000 series msi cell library. as is shown in table 7-1, it is calculated by multiplying the typ. value for v dd = 3.3 v by 1.11. table 7-1 delay coef?ient m (used for all cells excluding pre-driver with level shifter) 7.2 load due to input capacitance (load a) cell propagation delay is dependent upon the sum of input pin capacitances (load a) attached to the cells output terminal (i.e. the sum of the fan-ins). the input capacitances (fan-ins) of each gate and the output terminal load constraints (fan-outs) are listed in the ?ate array S1L35000 series msi cell library. cell output terminal fan-out must not exceed the listed max. value. a load a calculation example is shown in figure 7-1 and table 7-2. figure 7-1 example calculating load a conditions m value usage m min. m ty p. m max. power supply voltage: 5.0 v ?5%; ta: 0 to 70 o c 0.59 1.00 1.62 use after multiplying the typ. values of t 0 and k for v dd = 5.0 v power supply voltage: 5.0 v ?10%; ta: -40 to 85 o c 0.53 1.00 1.72 power supply voltage: 3.3 v ?10%; ta: 0 to 70 o c 0.51 1.00 1.82 power supply voltage: 3.3 v ?10%; ta: -40 to 85 o c 0.47 1.00 1.87 use after multiplying the typ. values of t 0 and k for v dd = 3.3 v power supply voltage: 3.0 v ?10%; ta: 0 to 70 o c 0.56 1.11 2.05 power supply voltage: 3.0 v ?10%; ta: -40 to 85 o c 0.51 1.11 2.10 xin 1 xin 2 xna 2 xno 2 2.1 1 1
chapter 7: propagation delay and timing gate array S1L35000 series epson 69 design guide table 7-2 data used in the example of calculating load a the fan-in values for xin2, xna2, and xno2 can be obtained from table 7-2. their sum is the load a value, as seen by the xin1 output terminal in load units (lu). load a (xin1) = (fan-in of xin2) + (fan-in of xna2) + (fan-in of xno2) = 2.1lu + 1lu + 1lu = 4.1lu 7.3 load due to interconnect capacitance (load b) the load resulting from the capacitance of the interconnect between cells (load b) cannot be accurately calculated until the asic layout has been performed. however, load b is correlated with the number of branches (number of nodes) connected to the wire, so it is possible to statistically estimate the load b value. the estimated interconnect capacitance for each master is listed in the ?ate array S1L35000 series msi library. cell input output pin fan-in pin fan-out xin1 a 1.0 x 23.4 xin2 a 2.1 x 49.3 xna2 a1 a2 1.0 1.0 x 22.7 xno2 a1 a2 1.0 1.0 x 12.3
chapter 7: propagation delay and timing 70 epson gate array S1L35000 series design guide 7.4 propagation delay calculations below we present a sample propagation delay time calculation using the circuit shown in figure 7-2 (assume an operating voltage of 5.0 v) and the data of table 7-3. figure 7-2 circuit for the sample calculation of the propagation delay time table 7-3 table of characteristics (power supply voltage = 5.0 v) cell input output t pd (typ.) pin fan- in pin fan- out from to edge t 0 (ps) k (ps/ lu) xin1 a 1.0 x 23.4 a x 76 40.8 70 20.8 xin2 a 2.1 x 49.3 a x 56 19.4 64 10.4 xna2 a1 1.0 x 22.7 a x 115 40.6 97 30.8 xno 2 a1 1.0 x 12.3 a x 129 72.2 97 20.7 xno 2 a p b c d xin 1 xin 2 xna 2 1 1 2.1
chapter 7: propagation delay and timing gate array S1L35000 series epson 71 design guide for this example, assume that load b of node p = 2 (lu), and assume that load b of nodes b, c and d = 0 (lu). also, note that propagation delay varies depending on the output terminal state transition (rising or falling edge). below please ?d examples calculating the propagation delays for paths a to p, a to b, a to c and a to d for both rising and falling cases under typ. operating conditions at 5v. 1. path a top: t pd = t pd (xin1) t pd (a rising to p falling ) = t 0 + k x (load a + load b) = 70 + 20.8 x (4.1 + 2) = 196.9 (ps) t pd (a rising to p falling )= t 0 + k x (load a + load b) = 76 + 40.8 x (4.1 + 2) = 324.9 (ps) 2. path a to b: t pd = t pd (xin1) + t pd (xin2) t pd (a rising to b rising )= t pd (a rising to p falling ) + t pd (p falling to b rising ) = 196.9 + t 0 = 196.9 + 56 = 252.9 (ps) t pd (a falling to b falling )= t pd (a falling to p rising ) + t pd (p rising to b falling ) = 324.9 + t 0 = 324.9 + 68 = 388.9 (ps) 3. path a to c: t pd = t pd (xin1) + t pd (xna2) t pd (a rising to c rising )= t pd (a rising to p falling ) + t pd (p falling to c rising ) = 196.9 + t 0 = 196.9 + 115 = 311.9 (ps) t pd (a falling to c falling )= t pd (a falling to p rising ) + t pd (p rising to c falling ) = 324.9 + t 0 = 324.9 + 97 = 421.9 (ps) 4. path a to d: t pd = t pd (xin1) + t pd (xno2) t pd (a rising to d rising )= t pd (a rising to p falling ) + t pd (p falling to d rising ) = 196.9 + t 0 = 196.9 + 129 = 325.9 (ps) t pd (a falling to d falling )= t pd (a falling to p rising ) + t pd (p rising to d falling ) = 324.9 + t 0 = 324.9 + 97 = 421.9 (ps)
chapter 7: propagation delay and timing 72 epson gate array S1L35000 series design guide 7.5 calculating output buffer delay as was discussed in chapter 4, all of the output buffers are isolated from the pre-drivers in the S1L35000 series. because of this, the output buffer delay times are the sum of the output cell delay times and the pre-driver delay times. assuming that the load capacitance connected to the output buffer is c l , the delay time t pd is calculated as follows: t pd = t 0 (output cell) + k (output cell) x c l /10 + t 0 (pre-driver) + k (pre-driver) x output cell input capacitance t 0 (output cell): the intrinsic delay of the output cell [ps] t 0 (pre-driver): the intrinsic delay of the pre-driver [ps] k (output cell): the output cell load delay coef?ient [ps/10 pf] k (pre-driver): the pre-driver load delay coef?ient [ps/lu] c l : the attached load capacitance [pf] please reference the ?ate array S1L35000 series msi cell library regarding the intrinsic delays and load delay coef?ients of the output cells and pre-drivers. 7.6 sequential cell setup/hold time a critical factor to analyze when designing an asic is sequential cell usage and operation. data which is to be stored by sequential logic must arrive before the gating or clock signal to insure suf?ient data setup and proper operation. that same data must remain unchanged or held subsequent to the gating or clock signal. these timing rules and others (see below) must be taken into consideration when designing sequential logic. sequential cell speci? timing values can be found in the ?ate array S1L35000 series msi cell library. (1) min. pulse width: tpwc, tpws or tpwr the min. pulse width refers to the min. value of the time between a leading edge and a trailing edge of an input pulse waveform, as seen at the clock, set, preset or reset terminal of a sequential cell. circuit malfunction may occur when a narrow pulse is applied which volates this constraint. the min. pulse widths may be of the following three types: t pwc : clock signal min. pulse width violation. t pws : set signal min. pulse width violation. t pwr : reset signal min. pulse width violation.
chapter 7: propagation delay and timing gate array S1L35000 series epson 73 design guide (2) setup time: teror/setup ?etup time refers to the required time interval in which the data state must be set before the active edge transition of the gate or clock signal in order to correctly store the data in a sequential cell or an msi function which is made up of sequential cells. (3) hold time: teror/hold ?old time refers to the required time interval in which the data state must be held after the active edge of the gate or clock signal in order to correctly store the data in a sequential cell or an msi function which is made up of sequential cells. (4) release time (setup): csero, crero/setup ?elease time (setup) refers to the required time interval between a set/reset signal transi- tion to inactive and the active edge of the gate or clock signal in a sequential cell of an msi function which is made up of sequential cells. (5) release time (hold): csero, crero/hold ?elease time (hold) refers to the required time interval between a set/reset signal transition to active and the active edge of the gate or clock signal in a sequential cell or an msi func- tion which is made up of sequential cells. (6) set/reset (setup): rsero/setup ?et/reset (setup) refers to the required time interval after a set input state is released until it is possible to have a rising edge on a reset input in a sequential cell or msi function which is made up of sequential cells. (7) set/reset (hold): rsero/hold the ?et/reset (hold) refers to the required time interval after a reset input state is released until it is possible to have a rising edge on a set input in a sequential cell or msi function which is made up of sequential cells.figure 7-3 xdfsr (example) figure 7-3 xdfsr (example) d c s r q xq data clock reset set q xq
chapter 7: propagation delay and timing 74 epson gate array S1L35000 series design guide figure 7-4 timing wave form (explanatory diagram for numbers 1-5) figure 7-5 timing wave form (explanatory diagram for numbers 6-7) tpwc tpwc setup (teror) hold (teror) release (hold) (crero) tpws (tpwr) release (setup) (crero) tpws (tpwr) clock data set (reset) set (reset) release (hold) (rsero) release (setup) (rsero) set set reset
chapter 7: propagation delay and timing gate array S1L35000 series epson 75 design guide table 7-4 dfsr timing characteristics (example) note : p = transition from 0 to 1 level or positive pulse n = transition from 1 to 0 level or negative pulse 7.7 chip internal skew because of transistor characteristic variance within an asic, the tpd of similar gates within an asic may vary. skew is a term used to describe this variance. skew must be taken into account so as to provide margin in timing critical portions of logic to insure proper operation. table 7-5 skew within the chip pin setup time1 t su (ps) hold time,t h (ps) pulsewidth, t w (ps) setup time, t su (ps) hold time, t h (ps) pulsewidth, t w (ps) typ.(v dd =5.0v) typ.(v dd =5.0v) typ.(v dd =5.0v) typ.(v dd =3.3v) typ.(v dd =3.3v) typ.(v dd =3.3v) c(p) to d 952 360 - 1388 516 - c(p) to s 609 710 - 871 1028 - c(p) to r 740 681 - 1058 989 - r(p) to s(p) 877 668 - 1222 949 - c(p) - - 1249 - - 1813 c(n) - - 1286 - - 1823 s(n) - - 1356 - - 1903 r(n) - - 1224 - - 1736 cell layout area skew internal cells all regions 5% i/o cell all regions 5%
chapter 8: test pattern generation 76 epson gate array S1L35000 series design guide chapter 8 test pattern generation test patterns must be generated once the logical design has been completed. test patterns are used to simulate and verify circuit functionality. test patterns are also used for product inspection prior to shipment. please keep the following guidelines in mind when generating test patterns, thereby improving manufacturability and insuring product quality. 8.1 testability considerations because the test pattern is used in the ?al inspection of the product before it is shipped, it must be able to test all circuits within the lsi. if there are areas within the circuits of the lsi which are untested, it will not be possible to test those areas before the product is shipped, and thus there will be the danger of shipping defective product. it is dif?ult to test all of the circuits within the lsi, so it is important to consider testability during the process of designing the circuit. 8.2 waveform types although the test pattern is normally a series of ? and ? when a simulation is performed or the lsi tests are run, the input wave forms can be delayed, and the wave forms can be changed. the wave forms which can be used when the test pattern is generated include the following two types: figure 8-1 constraints on timing settings nrz (non return to zero) a signal whose state changes no more than once per test pattern cycle is de?ed as being an nrz type waveform. this waveform type can be delayed by a constant offset from the beginning of the test pattern cycle boundary. nrz wave rz wave output wave strobe test cycle input delay pulse width
chapter 8: test pattern generation gate array S1L35000 series epson 77 design guide rz (return to zero) a signal whose state may change twice per test pattern cycle is de?ed as being an rz type waveform. this waveform type can be delayed by a constant offset from the beginning of the test pattern cycle boundary. this waveform type is useful for de?ing clock signals using positive or negative pulse de?itions. 8.3 constraints on the types of test patterns during design veri?ation, test patterns can be set to accurately re?ct actual operating frequency, yet in order to be used in ?al device inspection, the test patterns must adhere to constraints of the lsi tester. these constraints are explained below and should be kept in mind during test pattern development. 8.3.1 test period the test period must be 100 nsec or longer in duration and is de?ed in 1 nsec intervals. (recommended test period: 200 nsec.) 8.3.2 input delay (a) range of input delays 0 nsec < input delay value < strobe point. the input delay is de?ed in 1 nsec intervals within the range above. see section 8.3.5 below regarding constraints on the strobe point. (b) input delay values must have a min. of 5 nsec resolution from one another. (c) types of input delays no more than 8 types of input delays can be used in a single test pattern. a 0 ns delay is also counted as 1 type. when there are identical delays on an rz wave form as on an nrz wave form, these are counted as different delay types. when 2 rz wave forms have identical delay values or 2 nrz wave forms have identical delay values, these are counted as identi- cal delay types. (d) constrains on the ldi tester the test patterns are constrained by the lsi tester. refer to the qchapter 6.2 about the con- strains. 8.3.3 pulse width pulse widths for rz wave forms must be 15 nsec or more.
chapter 8: test pattern generation 78 epson gate array S1L35000 series design guide 8.3.4 input waveform format the input wave form must assume a value of ?? ?? ?? or ?? ? and ? indicate rz positive pulse and negative pulse type. use state ? to disable positive pulse rz waveform, and state ? to disable negative pulse rz waveform (i.e. rz type state combinations of (0,p) and (1,n) are valid, while state combinations of (0,n) and (1,p) are invalid). do not use a bi-directional pin as the clock. 8.3.5 strobe the constraints on the strobe are as follows. (a) only a single strobe may be used within a single test pattern event. (b) the smallest value for a strobe should be at least 30 nsec after the completion of all output signal changes, where the change results from input signals state change applied during that event. (c) the max. value for the strobe should be the test period minus 15 nsec. (d) the strobe is de?ed in 1nsec intervals. 8.4 notes regarding dc testing the test pattern is used for functional testing and dc testing of the lsi. please generate the test patterns so that the following dc tests can be performed. dc tests are performed to verify the dc parameters of the lsi. because the dc tests perform measurements on the trailing edge of the measurement events, those terminals which are measured must not have state changes after the strobe during the measurement events. the dc parameters measured are as described below: (a) output driver test (v oh , v ol ) the output buffer current driving capabilities are tested. the terminals which are to be tested are caused to enter the output level through the operation of the device, the speci?d current load is applied, and the level of the voltage drop is measured. in order to perform the output driver tests, it is necessary for the test pattern to cause all of the terminals to enter all of the states which are obtained when the device is operating. also, the states must be such that they do not change even if the measurement event extends the test period inde?itely. (b) quiescent current test (i dds ) the quiescent current is the leakage current which ?ws to the lsi power supply when the input is in an ?ed state. while generally this current is extremely small, this measurement must be done in a state where there are no other currents ?wing aside from the leakage current. to do this, all of the following conditions must be ful?led, and there must be two or more places wherein there are events which can measure the quiescent current.
chapter 8: test pattern generation gate array S1L35000 series epson 79 design guide (1) the input terminals are all in a ?ed state. (2) the bi-directional terminals are given ? level or ? level inputs or are in an output state. (3) there are no oscillators or operating functions within the circuit. (4) none of the internal 3-state buffers (internal bus) are in a ?ating or a contention state. (5) the ram, the rom, and the megacells are not in states wherein current is ?wing. (6) an ? level input is applied to input terminals which have pull-up resistors. (7) bi-directional terminals with pull-up resistors attached are either given ? level inputs or are producing ? level outputs. (8) bi-directional terminals with pull-down resistors are either in an input state or are pro- ducing ? level outputs. (c) the input current test the input current test measures the inputs to the input buffer. the test items include meas- urements of input leakage current and of pull-up/pull-down currents. the tests for these measurement items are performed by applying a v dd level or v ss level voltage to the termi- nal being measured, and measuring the current which ?ws. in other words, the test is per- formed by applying either an ? level or a ? level voltage to the terminal being measured. for example, when a v dd (? level) signal is applied during the test to a terminal being measured and which is in a state having an ? level, then there is the potential for this to cause the state to change from ? to ? in the terminal being measured, and the potential that this will cause the lsi to function incorrectly. in order to measure the input current tests, a test where a v dd level is applied at an event where there is an ? input to the terminal being measured in the test pattern, and a test is performed where a v ss level is applied in the event where a ? is applied. because of this, it is not possible to perform these tests when the terminals being measured are not in these states in the test pattern. the input current tests are further broken down into the following classi?ations. (1) input leakage current test (i lh . i ll ) measurements are performed regarding the input current of the input buffers which have no pull-up/pull-down resistors. the current which ?ws when an ? level voltage is applied to the input buffer is called i lh , and its max. current value is guaranteed. in order to perform this test there must be an event in the test pattern which causes the input terminal to be measured to have an ? level input. bi-directional terminals must have ? level inputs in the input state. the current which ?ws when a ? level voltage is applied to the input buffer is called i ll , and its max. value is guaranteed. in order to perform this test there must be an event in the test pattern which causes the input terminal to be measured to have a ? level input. bi-directional terminals must have ? level inputs in the input state.
chapter 8: test pattern generation 80 epson gate array S1L35000 series design guide (2) pull-up current tests (i pu ) this test measures the current which ?ws when an ? level voltage is applied to an input buffer having a pull-up resistance. in order to perform this test there must be an event in the test pattern which causes the input terminal to be measured to have an ? level input. bi-directional terminals must have ? level inputs in the input state. (3) pull-down current tests (i pd ) this test measures the current which ?ws when an ? level voltage is applied to an input buffer having a pull-down resistance. in order to perform this test there must be an event in the test pattern which causes the input terminal to be measured to have an ? level input. bi-directional terminals must have ? level inputs in the input state. (4) off state leakage current (i ozh , i ozl ) this measures the leakage current which ?ws when the output is a high-impedance state in output buffers which have open drains or which are 3-state output buffers. the actual measurement is the measurement of the currents when a v dd level voltage is applied, and when a v ss level voltage is applied to the terminal being measured when the terminal is in a high-impedance state. because of this, the terminal being meas- ured must enter into a high impedance state in the test pattern. 8.5 notes regarding the use of oscillation circuits an example of an oscillation circuit (oscillator, interval oscillator) is shown below. figure 8-2 example of oscillator circuits xlin xlot gate side signal drain side signal clock signal oscillation cell xlin xlot enable signal drain side signal clock signal oscillation cell gate side signal e g x d xin1 xin1 xin1 xna2 xna1 xna2
chapter 8: test pattern generation gate array S1L35000 series epson 81 design guide generally when oscillator circuits are used, the driving power of the oscillator inverter is small and the output wave form of the oscillator circuit is in?enced by the load of the measurement environment. thus the oscillator circuit is unable to transmit precise wave forms to the next-stage gates. because of this, in order to reproduce the conditions of the simulation in the tests, a procedure known as ?everse drive (i.e. a procedure wherein a signal having the same wave form as the output from the drain is input to the drain terminal) is used. when the oscillator inverter is structured as an inverter, it is possible to generate a reverse drive signal if the signal input from the drain is simply a reverse-phase input of the signal applied to the gate; however, in the case of nand gate structures (known as interval oscillators or gated-osc), then decisions cannot be made simply based on the gate signal alone, but rather the reverse drive wave form must be determined by looking at the expected values of the drain terminal. in this method, if the input wave form is the nrz wave form and the strobe is at the end of the test period, then the input wave form is put to the drain terminal expected value directly and a reverse drive wave form can be generated. however, in the case of the rz wave form, then the expected value of the drain terminal is ?ed to either an ? or an ? whether or oscillator is in a oscillating state or an oscillation stop state, so it is not possible to determine a reverse drive wave form by examining the expected state of the drain terminal. because of this, please keep the following cautions and notes in mind when a circuit having a interval oscillator is used: (1) an rz wave form cannot be used as the input signal. (2) do not cause transitions in the clock signal by transitions in the enable signal. 8.6 regarding ac testing ac testing measures the time it takes for a signal to propagate to the output terminal when there has been a transition at the input terminal during a single event. the ac testing can be performed on a measurement path selected by the customer. 8.6.1 constraints regarding measurement events because this test is done using a testing method known as the ?ormal binary search method, the terminal being measured (i.e. the output terminal wherein there is a transition) must have only a single transition point within a measurement event. (measurements cannot be performed on terminals having an rz wave form output, nor can they be performed in situations where a hazard is output during the measurement event.) also, the state transitions of the signal being measure must be either ? to ? or ? to ?? (transitions involving a high-impedance state cannot be measured.) other cautions and notes include the necessity for selecting events so that there are no signal contentions between the bi-directional terminals and the lsi tester, and that there are no situations where many output terminals have simultaneous transitions at the measurement event. this is because the lsi power source is overwhelmed when there are simultaneous transitions or signal contentions, affecting the output wave form of the terminals being measured and making it impossible to get an accurate measurement.
chapter 8: test pattern generation 82 epson gate array S1L35000 series design guide 8.6.2 constraints on the measurement locations for ac testing please use only 4 or less measurement locations in the ac testing. 8.6.3 constraints regarding the path delay which is tested the longer the delay in the ac measurement, the more accurate the measurement. the measurement path delay time should be recorded using max. delay simulation conditions targeting a path delay value of 30 nsec or more, and less than the strobe point. 8.6.4 other constraints (1) do not designate a path from the oscillator circuit. (2) designate a path which does not pass through a circuit having an internal 3-state unit (i.e. the internal bus). (3) do not designate a path passing through other bi-directional cells between the input cell and the output cell of the measurement path. (4) when there are two or more voltage ranges used, reconcile these to a single ac test meas- urement voltages. 8.7 test pattern constraints for bi-directional terminals by the constraints of testing, the bi-directional terminals cannot switch between input mode and output mode more than once within a single event. because of this, the test pattern generated should not use an rz wave form for controlling the bi-directional cell input/output mode switching. also, an rz wave form cannot be used as an input to the bi-directional terminal.
chapter 9: estimating the power consumption gate array S1L35000 series epson 83 design guide chapter 9 estimating the power consumption cmos lsis consume very little current when they are not operating. however, when they are operating, the power they consume depends on the operating frequency. when the power con- sumed is large, then the temperature of the lsi chip increases, and the quality of the lsi can be negatively affected if the temperature of the chip gets too high. because of this, it is necessary to calculate the power consumption and to check whether or not the power consumption is within allowable tolerances. 9.1 calculating the power consumption the power consumption of a cmos circuit is generally dependent on the operating frequency, the capacitance, and the power supply voltage. (this excludes those special situations where there is a normal current through ram/rom, etc.) here the cmos gate array power consumption can be calculated easily if the operating frequencies and load captaincies of the various cells used within the circuit are known. however, because it is dif?ult to calculate the load captaincies for each internal cell, use the rough calculations described below. after the power consumption for the input cells, the output cells and the internal cells are calcu- lated, and these values are summed to produce the total power consumption. (1) the input cell power consumption (p i ) the input cell power consumption is the sum of the products of the signal frequencies (mhz) input into each cell, and the input buffer power coef?ient k pi (?/mhz) for each cell. . k pi : input buffer power coef?ient (reference table 9-1 below) f i : the operating frequency of the ith input cell (mhz) table 9-1 k pi of input cells in the S1L35000 series. v dd (typ.) k pi 5.0 v 25 w/mhz 3.3 v 9.7 w/mhz 3.0 v 7.7 w/mhz p i = i=1 k (k pi x f i ) (w)
chapter 9: estimating the power consumption 84 epson gate array S1L35000 series design guide (2) output cell power consumption (po) the output cell power consumption differs depending on whether the load is a direct current load (such as resistive loads, ttl device connections, etc.) or whether the loads are alternating current loads (such as capacitance loads, cmos device connec- tions, etc.). in the case of alternating current loads, the output cell power consumption is calcu- lated from the load capacitance c l as follows: ?alternating current power consumption p ac = f x c l x (v dd ) 2 (w) f: output cell operating frequency (hz) c l : load capacitance (f) v dd : power supply voltage (v) in the case of the direct current load, the power consumed in the direct current load is added to the power consumed in the alternating current load. ?direct current power consumption p dc = p dch + p dcl where, p dch = |i oh | x (v dd - v oh ) (w) p dcl = i ol x v ol (w) the ratio of p dch and p dcl is determined by the output signal duty cycle. figure 9-1 example of the duty cycle duty h = (t 1 + t 2 ) / t duty l = (t - t 1 - t 2 ) / t because of this, p dc = p dch + p dc t t2 t2 = i=1 k {(v dd -v ohi ) x i ohi x duty h} + {v oli x i oli x duty l} k i=1
chapter 9: estimating the power consumption gate array S1L35000 series epson 85 design guide consequently, the power consumption p 0 of the output cell is calculated by: (3) internal cell power consumption (p int ) the internal cell power consumption depends on the type of device used, the cell use ef? ciency, the operating frequency, and the ratio of cells operating at the operating frequency. it is calculated as follows: nb: total number of bcs in the device type used. u: cell use ratio (use 50% to 60%) ? operating frequency of the ith group (mhz) s pi : percentage of cells operating at frequency ? (use 20% to 30%, though it depends on system.) k pint : internal cell power coef?ient (please reference table 9-2 below.) table 9-2 kpint of internal cells in the S1L35000 series because of this, the total power consumption p total is calculated as follows: p total = p i + p o + p int v dd (typ.) k pi 5.0 v 2.4 w/mhz 3.3 v 0.91 w/mhz 3.0 v 0.77 w/mhz po = (p ac + p dc ) = {fi x c li x (v dd ) 2 } + {(v dd - v ohi ) x i ohi x duty h} k i=1 k i=1 + {v oli x i oli x duty l} k i=1 p int = { (nb x u) x fi x s pi x (k pint ) } (w) k i=1
chapter 9: estimating the power consumption 86 epson gate array S1L35000 series design guide 9.2 constraints on power consumption the lsi chip heats up according to the power consumption within the lsi. the temperature of the lsi chip when it is mounted in a package can be calculated from the ambient temper- ature ta, the thermal resistance( j-a ) of the of the package, and the power consumption p d . the chip temperature (t j ) = ta + (p d x j-a ) ( o c) in normal use, the chip temperature (t j ) should be less than about 85 o c. please reference table 9-3 for the thermal resistances of each of the various packages. because the thermal resistances listed in table 9-3 are thermal resistances in a situation where there is no air circulation, these values will change substantially depending on the mounting of the packages on the circuit board and depending on whether or not there is forced air cooling. table 9-3 thermal resistances of various packages (without air circulation) qfp5 qfp5 qfp8 qfp8 qfp12 qfp13 qfp14 qfp15 tqfp14 tqfp14 tqfp15 pin 100 128 128 208 48 64 80 100 80 100 100 110 ( c/w) 110 65 45 230 170 110 115 100 100 110 alloy42 j-a j-a j-a 0 m/sec 1 m/sec 2 m/sec 3 m/sec 75 75 50 60 60 45 55 55 35 qfp20 144 85 70 50 40 qfp5 qfp5 qfp5 qfp8 qfp8 qfp10 qfp12 qfp13 qfp14 qfp15 qfp20 qfp21 qfp21 qfp22 qfp22 qfp23 qfp23 tqfp12 tqfp13 tqfp15 tqfp24 hqfp5 h2qfp23 h3qfp15 80 100 128 160 256 304 48 64 80 100 184 176 216 208 256 184 240 48 64 128 144 128 240 128 85( c/w) 80 80 45 50 35 175 130 110 90 65 55 55 45 45 40 40 165 140 105 80 60 30 85 cu-l/f 0 m/sec 1 m/sec 2 m/sec 3 m/sec 55 55 55 32 20 120 80 35 35 45 35 35 25 16 90 55 25 25 40 30 30 23 80 50 23 23 hqfp8 160 32 19 12 10 h2qfp8 208 34 pbga pbga pbga 225 256 388 72( c/w) 53 45 pbga 0 m/sec 1 m/sec 2 m/sec 3 m/sec 46 33 37 25 j-a j-a j-a j-a j-a j-a j-a j-a j-a pkg pin pkg pin pkg cflga424 cflga307 cflga239 cflga152 cflga104 75mm 50mm 30mm 75mm 50mm 30mm 75mm 50mm 30mm 75mm 50mm 30mm 75mm 50mm 30mm cflga 3.82 mm 3.82 mm 5.73 mm 5.73 mm chip size 44.0 ( c/w) 46.9 61.1 44.0 47.1 61.7 44.0 47.3 62.2 44.8 48.8 63.3 45.5 50.3 64.3 32.9 36.4 50.1 33.1 37.4 51.5 33.1 38.3 52.9 34.4 39.7 53.9 35.6 41.1 54.9 24.6 27.8 42.1 24.9 28.5 43.1 25.1 29.2 43.9 9.55 mm 9.55 mm customer s board size (board installation under the windless condition) package type
chapter 10: pin layout considerations gate array S1L35000 series epson 87 design guide chapter 10 pin layout considerations 10.1 estimating the number of power supply terminals it is necessary to estimate the number of power supply terminals required based on the power consumed by the lsi and on the number of output buffers. the output buffers use a large current when switching. the number of power supply terminals required by the lsi can be estimated by its relationship with the current consumed as shown below. if the current consumed is i dd (ma), then the number of power supply terminals required (n idd ) to supply the consumption current i dd is as follows: n idd i dd /50 (pairs) note: insert at least two pair of power terminal n idd . i dd : calculate i dd by dividing the power consumption calculated in chapter 9 by the oper- ating voltage. 10.2 number of simultaneous operations and adding power supplies in the S1L35000 series, the output drive capability is extremely large at a max. of 12 ma, and thus the noise generated by the output buffers when they are operating is also extremely large. v ss power supplies need to be added, as shown in table 10-1 to prevent malfunction from the noise when multiple output buffers operate at the same time. moreover, add v dd terminals at 1-to-1 ratio with additional v ss terminals. (see table 10-2.)
chapter 10: pin layout considerations 88 epson gate array S1L35000 series design guide table 10-1 number of v ss power supplies to add depending on the simultaneous operation of output buffers (v dd =5v) note: when using power of 3.0v dd or 3.3v dd (typ.), the number of output buffers should be about 60% of the number metioned above list. table 10-2 number of v dd power supplies to add depending on the simultaneous operation of output buffers (v dd =5v) note: when using power of 3.0v dd or 3.3v dd (typ.), the number of output buffers should be about 60% of the number metioned above list. output drive ability (i ol ) number of output buffers operating simultaneously number of additional power supplies c l < 50pf c l < 100pf c l < 200pf 8ma < 8012 < 16 1 2 4 < 24 1 3 6 < 32 2 4 8 12ma < 8123 < 16 2 3 5 < 24 2 5 7 < 32 3 6 12 output drive ability (i oh ) number of output buffers operating simultaneously number of additional power supplies c l < 50pf c l < 100pf c l < 200pf 8ma < 8011 < 16 1 1 3 < 24 1 2 4 < 32 1 3 5 12ma < 8123 < 16 2 3 4 < 24 2 4 5 < 32 3 5 9
chapter 10: pin layout considerations gate array S1L35000 series epson 89 design guide 10.3 cautions and notes regarding the layout of terminals once the package to be used has been selected, then it is time to layout the pins. please see the speci? ?in layout table regarding the number of power supply pins and useable input/output terminals in the various S1L35000 series packages. once the pin layout has been established, submit to epson a pin assignment speci?ation which has been ?led out with the pin layout. epson will layout the interconnections according to the speci?ation submitted by the customer, so we request that the customer carefully check this speci?ation. the pin layout is one of the critical speci?ations which controls the quality of the lsi. it is espe- cially important in avoiding malfunctions due to noise. moreover, problems with noise are dif?ult to check for in simulations. so that there will be are no malfunctions with non-traceable causes in the customers lsi, we urge the customer to carefully study the guidelines detailed in this chapter before generating the pin layout. 10.3.1 fixed power supply pins there are some pins which can only be used for power supply, depending on the combination of each device and package in this series. because there are some pins which must be set to v dd pins and some pins which must be set to v ss pins please consult with epson when selecting a package. 10.3.2 cautions and notes regarding the pin layout the pin layout in?ences the logical functioning and electrical characteristics of the lsi. moreo- ver, the pin layout may be constrained by the construction of the lsi, the structuring of the cells and the bulk, etc. because of this, we will explain factors which must be researched when creat- ing the pin layout, factors such as the power supply current, the input pin/output pin isolation, the critical signals, the pull-up/pull-down resistor inputs, simultaneous output, current drivers, etc. (1) power supply current (i dd , i ss ) when it comes to the power supply current (i dd , i ss ) there are limitations on the tolerable lev- els for current from the power supply through the power supply pins when in an operating state. when the tolerable levels are exceeded, the current density within the power supply interconnects within the lsi becomes too high, and the voltage generated by the current and the resistance within the interconnects increases or decreases. this may lead to malfunc- tioning and may have an impact on dc or ac characteristics in order to avoid these types of problems, it is necessary to reduce the current density and the power supply interconnect line impedance. to do this, it is necessary to estimate the power consumption during the design of the gate array, and to make sure that there are enough power supply pins so that the current through each of the power supply pins does not exceed tolerances. moreover, the layout should be such that the power supply pins are not concentrated all in one location, but rather are spread out.
chapter 10: pin layout considerations 90 epson gate array S1L35000 series design guide however, the ?al power supply pin count may require the addition of power supply pins according to the above, and the power supply pin count must include additional power supply pins for the purpose of reducing noise, etc. see section 10.1, ?umber of simultaneous operations and adding power supplies, regarding additional the number of additional power supply pins. (2) noise resulting from the operation of output cells the noise resulting from the operation of the output cells can be broadly divided into two cat- egories. to reduce this noise as many power supplies should be added as possible as the countermeasure. a) noise generated in the power supply lines when many outputs switch simultaneously, there will be problems with noise gener- ated in the power supply line. this can change the lsi input threshold levels, causing malfunctions. this power supply line noise is a result of the large current which is caused to ?w in the power supply lines when output cells switch simultaneously. the power supply noise exerts an especially large impact on the interface components. because of this, the lsi equivalent circuits can be represented as shown in figure 10- 1. the output of this circuit diagram shows that when there is an ? to ? transition, the current from the output pin ?ws through the components within the lsi, and ?ws through the equivalent inductance l 2 of the lsi package, etc. at this time, the voltage in the v ss power supply line within the lsi is distorted by the equivalent inductance l 2 . this voltage distortion in the v ss power supply line is the noise that is generated within the power supply line. the noise which is generated within the power supply lines is primarily a result of the equivalent inductance l 2 , so a large amount of noise is gener- ated when power supply currents change rapidly.
chapter 10: pin layout considerations gate array S1L35000 series epson 91 design guide figure 10-1 an lsi equivalent circuit b) overshoot, undershoot, ringing the equivalent inductance in the output pins causes noises known as ?vershoot, ?ndershoot and ?inging. this equivalent inductance is marked by l 3 in figure 10-1. because inductance has the property of storing energy, this overshoot, undershoot or ringing is the result of the output becoming either low or high. when there is a transi- tion, the overshoot and undershoot is proportional to the size of the current to the rate of change of the current. the most effective way to reduce overshoot and undershoot is to use output cells with relatively small drive current, and there is a tendency for the overshoot and under- shoot to be reduced when there is a relatively large load capacitance. because of this, there is a need for caution when using cells with especially large current driving capabilities. (3) isolating input pins and output pins separating the input pin group from the output pin group in the pin layout is an important technique for reducing the impact of noise. because input pins and bi-directional pins in the input state are especially susceptible to noise, one should avoid mixing these pins with output pins whenever possible, and the input pin group, the output pin group, and the bi-directional pin group should be separated from each other by the power supply pins (v dd , v ss ). v dd v dd (internal) v ss (internal) l 1 l 2 l 3 v 1 output pin
chapter 10: pin layout considerations 92 epson gate array S1L35000 series design guide figure 10-2 example of separating input pins and output pins (4) critical signals the following cautions and notes should be kept in mind when laying out the pins for critical signals such as clock input pins and high-speed output pins. a) pins for which it is necessary to reduce the noise, such as clock and reset pins, should be placed near the power supply pins and far from the output pins. (see figure 10-3) b) oscillator circuit pins (oscin, oscout) should be placed near one another, sand- wiched between power supply pins (v dd , v ss ). moreover, they should not be placed near output pins. (see figure 10-4.) c) high-speed input and output pins should be placed near the center of the edge of the chip (of the package). (see figure 10-3.) d) when there is little margin in the customer speci?ations for delays between the input pins and the output pins, these input and output pins should be placed near to one another. (see figure 10-3.) figure 10-3 example 1 of a layout for critical signals v dd v ss v dd v dd v dd v dd v dd v ss v ss v ss v ss v ss output pins output pins input pins bid pins rst clk v ss v ss high speed input through input through output high speed output
chapter 10: pin layout considerations gate array S1L35000 series epson 93 design guide figure 10-4 example 2 of a layout for critical signals (5) pull-up/pull-down resistor inputs the pull-up and pull-down resistance values are relatively large, ranging from a few dozen to a few hundred kohms. the structure of the resistors depends on the power supply voltage. because of this, the pins are especially vulnerable to noise coming from the power supply. the following cautions should be carefully considered when creating the pin layout in order to prevent this noise from causing malfunctions. a) locate as far as possible from high-speed inputs (such as clock pins). (see figure 10-5.) b) locate away from output pins (especially large-current output pins). (see figure 10-6.) please consider the following points prior to pin layout. ?perform pull-up and pull-down processes on the pcb itself whenever possible. ?select resistors with low resistances whenever possible. \ figure 10-5 example 1 of placement of pull-up and pull-down resistors figure 10-6 example 2 of placement of pull-up and pull-down resistors v ss osc in v dd v ss osc out clk pull up pull down high drive output
chapter 10: pin layout considerations 94 epson gate array S1L35000 series design guide (6) simultaneous switching of outputs noise is generated when multiple output pins change at the same time, which may cause mal- functioning of the lsi. in order to reduce the risk of malfunction due to noise when multiple output pins change at the same time, a power supply pin should be added to the group of output pins which are changing simultaneously. see section 10.2 regarding the number of power supply pins which must be added and the method for laying out these power supply pins. in order to reduce this noise, one may alternatively add a cell to delay the previous stage of these output cell groups, thereby reducing the amount of simultaneous changes of the output cells, thereby reducing noise as well. (see figure 10-8.) figure 10-7 example of adding power supply pins figure 10-8 example of adding delay cells (7) large current drivers when outputs are used which drive large currents (i ol = 12 ma ), pin layout should be per- formed following the constraints below: a) constraints on strengthening the power supplies power supply pins should be located near the large-current driver pins to minimize switching niose. (see figure 10-9.) b) low-noise pre-drivers low-noise output cells and low-noise pre-drivers have been prepared in order to reduce the noise generated by the operation of output cells with large current drivers. see chapter 4 regarding recommended combinations of pre-drivers and output cells. v dd v ss v dd v ss v dd v ss v ss v ss simultaneously changing output pins. a td ts p n xpdv1t xuo3 a td ts p n xpdv1t xdl1 xuo3 out1 out2
chapter 10: pin layout considerations gate array S1L35000 series epson 95 design guide figure 10-9 example of strengthening power supplies (8) other cautions and notes the relationship between the package pins and the lsi pads is already established by the combination of each series device type and package type. because of this, there may be constraints on the use of pins because of the package, and constraints on the pin layout due to the i/o cell types. notes and cautions regarding these restraints are described below; these should be kept in mind when determining the pin layouts. a) nc pins (non-connection) a pin might be unavailable for use when the number of pads on the lsi is less than the number of pins on the package, or when the lsi pad cannot be connected to one of the package pins. mark these with a double asterisk (**) on the pin layout table. v ss v ss high drive output
chapter 10: pin layout considerations 96 epson gate array S1L35000 series design guide 10.3.3 examples of recommended pin connections the pin layout is a critical point in ensuring that the lsi operates correctly. determine pin layouts after referencing the example pin layout (figure 10-10) which takes into consideration the entire content explained in this chapter. figure 10-10 example of recommended pin layout input pins are located on the upper and left hand edges of the package, output pins which change simultaneously are located on the right hand side of the package, and bi-directional pins and other output pins are located on the bottom edge of the package. v dd v ss input pins output pins input pins plup inp9 inp10 inp11 inp14 inp15 inp16 inp17 inp18 inp19 v dd inp12 inp13 clk v dd v ss sout0 sout1 sout2 sout5 sout6 sout7 sout8 sout9 sout3 sout4 v ss v ss v ss v ss inp8 v ss v ss v dd v ss v ss inp7 inp6 inp5 inp4 inp3 inp2 inp1 inp0 oscin oscout v dd v dd v ss v ss bid0 hout v ss bid1 bid2 bid3 bid4 v ss v ss out0 out1 mosc output pins bid pins
chapter 10: pin layout considerations gate array S1L35000 series epson 97 design guide table 10-2 pin layout example location pin name explanation of pin name detailed explanation of the position of each pin upper edge pulp clk input pins with pull-ups input pins for the clock located where the impact of noise is the least. located near the center of the package, and near power supply pins. left edge oscin, oscout inp0 to19 oscillator pins input pins located near the center of the package, and near power supply pins. located with power supply pins, away from other pins. right-hand edge sout0 to 9 simultaneously changing output pins located near power supply pins and separated from other pins with additional power supply pins. bottom edge bid0-4 mosc hout out01 bi-directional pins oscillator monitor output pins high-drive output pins output pins located near power supply pins and separated from other pins. located separated from oscillator pins and near power supply pins. located near power supply pins. located near power supply pins and separated from other pins. all edges v dd v ss v dd power supply pins v ss (gnd) power supply pins
chapter 10: pin layout considerations 98 epson gate array S1L35000 series design guide simulation input timing waveforms *the about timing might change with the limitation of the measuring system including a tester. a file name type waveform input pin name nrz b nrz c nrz d nrz nrz strobe ? system clock strobe point rate a.p a.p a.p = active point a b c d e rate (ns) comment delay (ns) (system clock) duty
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design guide S1L35000 series first issue march,2000 d printed april, 2001 in japan c a epson electronic devices website electronic devices marketing division http://www.epsondevice.com document code: 404570102 this manual was made with recycle papaer, and printed using soy-based inks.

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